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-rw-r--r--techlibs/ice40/tests/test_arith.ys2
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index 7e928ec78..ddb80b700 100644
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -8,8 +8,6 @@ rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
-delete A:whitebox # Necessary since whiteboxes cannot
- # be overwritten...
synth_ice40 -top gate
read_verilog test_arith.v