3 files changed, 3 insertions, 38 deletions
diff --git a/techlibs/intel/cycloneiv/cells_arith.v b/techlibs/intel/cycloneiv/cells_arith.v
index f7bc3cd65..1241e89fe 100644
--- a/techlibs/intel/cycloneiv/cells_arith.v
+++ b/techlibs/intel/cycloneiv/cells_arith.v
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/techlibs/intel/cycloneiv/cells_map.v b/techlibs/intel/cycloneiv/cells_map.v
index 56d32e586..59f50bddb 100644
--- a/techlibs/intel/cycloneiv/cells_map.v
+++ b/techlibs/intel/cycloneiv/cells_map.v
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -19,41 +19,6 @@
 // > c60k28 (Viacheslav, VT) [at] yandex [dot] com
 // > Intel FPGA technology mapping. User must first simulate the generated \
 // > netlist before going to test it on board.
-// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed.
-
-// Normal mode DFF negedge clk, negedge reset
-module  \$_DFF_N_ (input D, C, output Q);
-   parameter WYSIWYG="TRUE";
-   parameter power_up=1'bx;
-   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Normal mode DFF
-module  \$_DFF_P_ (input D, C, output Q);
-   parameter WYSIWYG="TRUE";
-   parameter power_up=1'bx;
-   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-
-// Async Active Low Reset DFF
-module  \$_DFF_PN0_ (input D, C, R, output Q);
-   parameter WYSIWYG="TRUE";
-   parameter power_up=1'bx;
-   dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Async Active High Reset DFF
-module  \$_DFF_PP0_ (input D, C, R, output Q);
-   parameter WYSIWYG="TRUE";
-   parameter power_up=1'bx;
-   wire R_i = ~ R;
-   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-
-module  \$_DFFE_PP0P_ (input D, C, E, R, output Q);
-   parameter WYSIWYG="TRUE";
-   parameter power_up=1'bx;
-   wire E_i = ~ E;
-   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
-endmodule
 
 // Input buffer map
 module \$__inpad (input I, output O);
diff --git a/techlibs/intel/cycloneiv/cells_sim.v b/techlibs/intel/cycloneiv/cells_sim.v
index 2af2ab990..f3c8fbe03 100644
--- a/techlibs/intel/cycloneiv/cells_sim.v
+++ b/techlibs/intel/cycloneiv/cells_sim.v
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above