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-rw-r--r--techlibs/intel/arria10gx/cells_arith.v6
-rw-r--r--techlibs/intel/arria10gx/cells_map.v1
-rw-r--r--techlibs/intel/cyclone10lp/cells_arith.v6
-rw-r--r--techlibs/intel/cyclone10lp/cells_map.v3
-rw-r--r--techlibs/intel/cycloneiv/cells_arith.v6
-rw-r--r--techlibs/intel/cycloneiv/cells_map.v3
-rw-r--r--techlibs/intel/cycloneive/arith_map.v6
-rw-r--r--techlibs/intel/cycloneive/cells_map.v3
-rw-r--r--techlibs/intel/cyclonev/cells_arith.v6
-rw-r--r--techlibs/intel/cyclonev/cells_map.v3
-rw-r--r--techlibs/intel/max10/cells_arith.v6
-rw-r--r--techlibs/intel/max10/cells_map.v3
-rw-r--r--techlibs/intel/synth_intel.cc8
13 files changed, 51 insertions, 9 deletions
diff --git a/techlibs/intel/arria10gx/cells_arith.v b/techlibs/intel/arria10gx/cells_arith.v
index 89fb4561f..6a52a0f95 100644
--- a/techlibs/intel/arria10gx/cells_arith.v
+++ b/techlibs/intel/arria10gx/cells_arith.v
@@ -26,8 +26,11 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -36,11 +39,14 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
diff --git a/techlibs/intel/arria10gx/cells_map.v b/techlibs/intel/arria10gx/cells_map.v
index 1430e8551..83f5881da 100644
--- a/techlibs/intel/arria10gx/cells_map.v
+++ b/techlibs/intel/arria10gx/cells_map.v
@@ -30,6 +30,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/cyclone10lp/cells_arith.v b/techlibs/intel/cyclone10lp/cells_arith.v
index 5ae8d6cea..d8c46e865 100644
--- a/techlibs/intel/cyclone10lp/cells_arith.v
+++ b/techlibs/intel/cyclone10lp/cells_arith.v
@@ -26,8 +26,11 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -36,11 +39,14 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
diff --git a/techlibs/intel/cyclone10lp/cells_map.v b/techlibs/intel/cyclone10lp/cells_map.v
index c2f6f403c..25d73711c 100644
--- a/techlibs/intel/cyclone10lp/cells_map.v
+++ b/techlibs/intel/cyclone10lp/cells_map.v
@@ -48,7 +48,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/cycloneiv/cells_arith.v b/techlibs/intel/cycloneiv/cells_arith.v
index 010a4b5da..f7bc3cd65 100644
--- a/techlibs/intel/cycloneiv/cells_arith.v
+++ b/techlibs/intel/cycloneiv/cells_arith.v
@@ -70,8 +70,11 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -79,11 +82,14 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH < 6;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
diff --git a/techlibs/intel/cycloneiv/cells_map.v b/techlibs/intel/cycloneiv/cells_map.v
index 191488430..56d32e586 100644
--- a/techlibs/intel/cycloneiv/cells_map.v
+++ b/techlibs/intel/cycloneiv/cells_map.v
@@ -48,7 +48,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v
index 49e36aa25..a755e10db 100644
--- a/techlibs/intel/cycloneive/arith_map.v
+++ b/techlibs/intel/cycloneive/arith_map.v
@@ -66,8 +66,11 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -75,11 +78,14 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH < 5;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
diff --git a/techlibs/intel/cycloneive/cells_map.v b/techlibs/intel/cycloneive/cells_map.v
index abeb92eef..43a1183de 100644
--- a/techlibs/intel/cycloneive/cells_map.v
+++ b/techlibs/intel/cycloneive/cells_map.v
@@ -48,7 +48,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/cyclonev/cells_arith.v b/techlibs/intel/cyclonev/cells_arith.v
index 89fb4561f..6a52a0f95 100644
--- a/techlibs/intel/cyclonev/cells_arith.v
+++ b/techlibs/intel/cyclonev/cells_arith.v
@@ -26,8 +26,11 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -36,11 +39,14 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v
index f8d142bc9..8223df3c6 100644
--- a/techlibs/intel/cyclonev/cells_map.v
+++ b/techlibs/intel/cyclonev/cells_map.v
@@ -50,7 +50,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
wire VCC;
diff --git a/techlibs/intel/max10/cells_arith.v b/techlibs/intel/max10/cells_arith.v
index e2194cbd7..8529706a7 100644
--- a/techlibs/intel/max10/cells_arith.v
+++ b/techlibs/intel/max10/cells_arith.v
@@ -26,8 +26,11 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -36,11 +39,14 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
diff --git a/techlibs/intel/max10/cells_map.v b/techlibs/intel/max10/cells_map.v
index 6d604e072..55b393080 100644
--- a/techlibs/intel/max10/cells_map.v
+++ b/techlibs/intel/max10/cells_map.v
@@ -48,7 +48,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 8601ebb37..f3709498c 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SynthIntelPass : public ScriptPass {
SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { experimental(); }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -81,7 +81,7 @@ struct SynthIntelPass : public ScriptPass {
string top_opt, family_opt, vout_file, blif_file;
bool retime, flatten, nobram, iopads;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
family_opt = "max10";
@@ -93,7 +93,7 @@ struct SynthIntelPass : public ScriptPass {
iopads = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -163,7 +163,7 @@ struct SynthIntelPass : public ScriptPass {
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin")) {
if (check_label("family"))
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 08:24:45 +0000