1 files changed, 31 insertions, 10 deletions
diff --git a/techlibs/intel_alm/common/dff_sim.v b/techlibs/intel_alm/common/dff_sim.v
index 32444dd46..9ff8f9f67 100644
--- a/techlibs/intel_alm/common/dff_sim.v
+++ b/techlibs/intel_alm/common/dff_sim.v
@@ -53,23 +53,44 @@
 // Q: data output
 //
 // Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.
+
+`ifdef cyclonev
+`define SYNCPATH 262
+`define SYNCSETUP 522
+`define COMBPATH 0
+`endif
+`ifdef cyclone10gx
+`define SYNCPATH 219
+`define SYNCSETUP 268
+`define COMBPATH 0
+`endif
+
+// fallback for when a family isn't detected (e.g. when techmapping for equivalence)
+`ifndef SYNCPATH
+`define SYNCPATH 0
+`define SYNCSETUP 0
+`define COMBPATH 0
+`endif
+
+(* abc9_box, lib_whitebox *)
 module MISTRAL_FF(
     input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
     output reg Q
 );
 
-`ifdef cyclonev
-specify
-    (posedge CLK => (Q : DATAIN)) = 262;
-    $setup(DATAIN, posedge CLK, 522);
-endspecify
-`endif
-`ifdef cyclone10gx
 specify
-    (posedge CLK => (Q : DATAIN)) = 219;
-    $setup(DATAIN, posedge CLK, 268);
+    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = `SYNCPATH;
+    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = `SYNCPATH;
+    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = `SYNCPATH;
+
+    $setup(DATAIN, posedge CLK, `SYNCSETUP);
+    $setup(ENA, posedge CLK, `SYNCSETUP);
+    $setup(SCLR, posedge CLK, `SYNCSETUP);
+    $setup(SLOAD, posedge CLK, `SYNCSETUP);
+    $setup(SDATA, posedge CLK, `SYNCSETUP);
+
+    if (ACLR === 1'b0) (ACLR => Q) = `COMBPATH;
 endspecify
-`endif
 
 initial begin
     // Altera flops initialise to zero.