1 files changed, 43 insertions, 4 deletions
diff --git a/techlibs/intel_alm/common/dff_sim.v b/techlibs/intel_alm/common/dff_sim.v
index 32444dd46..8d58bf614 100644
--- a/techlibs/intel_alm/common/dff_sim.v
+++ b/techlibs/intel_alm/common/dff_sim.v
@@ -53,21 +53,60 @@
 // Q: data output
 //
 // Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.
+
+(* abc9_box, lib_whitebox *)
 module MISTRAL_FF(
-    input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
+    input DATAIN,
+    (* clkbuf_sink *) input CLK,
+    input ACLR, ENA, SCLR, SLOAD, SDATA,
     output reg Q
 );
 
 `ifdef cyclonev
 specify
-    (posedge CLK => (Q : DATAIN)) = 262;
-    $setup(DATAIN, posedge CLK, 522);
+    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
+    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
+    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618;
+
+    $setup(DATAIN, posedge CLK, /* -196 */ 0);
+    $setup(ENA, posedge CLK, /* -196 */ 0);
+    $setup(SCLR, posedge CLK, /* -196 */ 0);
+    $setup(SLOAD, posedge CLK, /* -196 */ 0);
+    $setup(SDATA, posedge CLK, /* -196 */ 0);
+
+    if (ACLR === 1'b0) (ACLR => Q) = 282;
+endspecify
+`endif
+`ifdef arriav
+specify
+    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 470;
+    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 633;
+    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 439;
+
+    $setup(DATAIN, posedge CLK, /* -170 */ 0);
+    $setup(ENA, posedge CLK, /* -170 */ 0);
+    $setup(SCLR, posedge CLK, /* -170 */ 0);
+    $setup(SLOAD, posedge CLK, /* -170 */ 0);
+    $setup(SDATA, posedge CLK, /* -170 */ 0);
+
+    if (ACLR === 1'b0) (ACLR => Q) = 215;
 endspecify
 `endif
 `ifdef cyclone10gx
 specify
-    (posedge CLK => (Q : DATAIN)) = 219;
+    // TODO (long-term): investigate these numbers.
+    // It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
+    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
+    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
+    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
+
     $setup(DATAIN, posedge CLK, 268);
+    $setup(ENA, posedge CLK, 268);
+    $setup(SCLR, posedge CLK, 268);
+    $setup(SLOAD, posedge CLK, 268);
+    $setup(SDATA, posedge CLK, 268);
+
+    if (ACLR === 1'b0) (ACLR => Q) = 0;
 endspecify
 `endif