diff options
Diffstat (limited to 'techlibs/intel_alm/common/dsp_sim.v')
-rw-r--r-- | techlibs/intel_alm/common/dsp_sim.v | 68 |
1 files changed, 58 insertions, 10 deletions
diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v index 5dc4c02de..bdb6d18d5 100644 --- a/techlibs/intel_alm/common/dsp_sim.v +++ b/techlibs/intel_alm/common/dsp_sim.v @@ -1,35 +1,83 @@ (* abc9_box *) -module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y); +module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + +// TODO: Cyclone 10 GX timings; the below are for Cyclone V specify - (A *> Y) = 4057; - (B *> Y) = 4057; + (A *> Y) = 3732; + (B *> Y) = 3928; endspecify -assign Y = $signed(A) * $signed(B); +wire [53:0] A_, B_; + +if (A_SIGNED) + assign A_ = $signed(A); +else + assign A_ = $unsigned(A); + +if (B_SIGNED) + assign B_ = $signed(B); +else + assign B_ = $unsigned(B); + +assign Y = A_ * B_; endmodule (* abc9_box *) module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + +// TODO: Cyclone 10 GX timings; the below are for Cyclone V specify - (A *> Y) = 4057; - (B *> Y) = 4057; + (A *> Y) = 3180; + (B *> Y) = 3982; endspecify -assign Y = $signed(A) * $signed(B); +wire [35:0] A_, B_; + +if (A_SIGNED) + assign A_ = $signed(A); +else + assign A_ = $unsigned(A); + +if (B_SIGNED) + assign B_ = $signed(B); +else + assign B_ = $unsigned(B); + +assign Y = A_ * B_; endmodule (* abc9_box *) module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + +// TODO: Cyclone 10 GX timings; the below are for Cyclone V specify - (A *> Y) = 4057; - (B *> Y) = 4057; + (A *> Y) = 2818; + (B *> Y) = 3051; endspecify -assign Y = $signed(A) * $signed(B); +wire [17:0] A_, B_; + +if (A_SIGNED) + assign A_ = $signed(A); +else + assign A_ = $unsigned(A); + +if (B_SIGNED) + assign B_ = $signed(B); +else + assign B_ = $unsigned(B); + +assign Y = A_ * B_; endmodule |