diff options
Diffstat (limited to 'techlibs/intel_alm/common')
| -rw-r--r-- | techlibs/intel_alm/common/bram_m10k.txt | 16 | ||||
| -rw-r--r-- | techlibs/intel_alm/common/bram_m10k_map.v | 16 | ||||
| -rw-r--r-- | techlibs/intel_alm/common/mem_sim.v | 2 | ||||
| -rw-r--r-- | techlibs/intel_alm/common/quartus_rename.v | 9 |
4 files changed, 29 insertions, 14 deletions
diff --git a/techlibs/intel_alm/common/bram_m10k.txt b/techlibs/intel_alm/common/bram_m10k.txt index e9355fe2c..560711b65 100644 --- a/techlibs/intel_alm/common/bram_m10k.txt +++ b/techlibs/intel_alm/common/bram_m10k.txt @@ -1,21 +1,15 @@ -bram MISTRAL_M10K +bram $__MISTRAL_M10K init 0 # TODO: Re-enable when I figure out how BRAM init works abits 13 @D8192x1 dbits 1 @D8192x1 abits 12 @D4096x2 dbits 2 @D4096x2 - abits 11 @D2048x4 @D2048x5 - dbits 4 @D2048x4 + abits 11 @D2048x5 dbits 5 @D2048x5 - abits 10 @D1024x8 @D1024x10 - dbits 8 @D1024x8 + abits 10 @D1024x10 dbits 10 @D1024x10 - abits 9 @D512x16 @D512x20 - dbits 16 @D512x16 + abits 9 @D512x20 dbits 20 @D512x20 - abits 8 @D256x32 @D256x40 - dbits 32 @D256x32 - dbits 40 @D256x40 groups 2 ports 1 1 wrmode 1 0 @@ -27,7 +21,7 @@ bram MISTRAL_M10K endbram -match MISTRAL_M10K +match $__MISTRAL_M10K min efficiency 5 make_transp endmatch diff --git a/techlibs/intel_alm/common/bram_m10k_map.v b/techlibs/intel_alm/common/bram_m10k_map.v new file mode 100644 index 000000000..8f9d4a3b3 --- /dev/null +++ b/techlibs/intel_alm/common/bram_m10k_map.v @@ -0,0 +1,16 @@ +// Stub to invert M10K write-enable. + +module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + +parameter CFG_ABITS = 10; +parameter CFG_DBITS = 10; + +input CLK1; +input [CFG_ABITS-1:0] A1ADDR, B1ADDR; +input [CFG_DBITS-1:0] A1DATA; +input A1EN, B1EN; +output reg [CFG_DBITS-1:0] B1DATA; + +MISTRAL_M10K #(.CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN)); + +endmodule
\ No newline at end of file diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v index 370e17f27..c9ba8c7f1 100644 --- a/techlibs/intel_alm/common/mem_sim.v +++ b/techlibs/intel_alm/common/mem_sim.v @@ -145,7 +145,7 @@ endspecify `endif always @(posedge CLK1) begin - if (A1EN) + if (!A1EN) mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA; if (B1EN) diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v index 5850f6907..217dc5de9 100644 --- a/techlibs/intel_alm/common/quartus_rename.v +++ b/techlibs/intel_alm/common/quartus_rename.v @@ -157,6 +157,11 @@ output [CFG_DBITS-1:0] B1DATA; // Much like the MLAB, the M10K has mem_init[01234] parameters which would let // you initialise the RAM cell via hex literals. If they were implemented. +// Since the MISTRAL_M10K block has an inverted write-enable (like the real hardware) +// but the Quartus primitive expects a normal write-enable, we add an inverter. +wire A1EN_N; +NOT wren_inv (.IN(A1EN), .OUT(A1EN_N)); + `RAM_BLOCK #( .operation_mode("dual_port"), .logical_ram_name(_TECHMAP_CELLNAME_), @@ -176,10 +181,10 @@ output [CFG_DBITS-1:0] B1DATA; .port_b_first_bit_number(0), .port_b_address_clock("clock0"), .port_b_read_enable_clock("clock0") -) _TECHMAP_REPLACE_ ( +) ram_block ( .portaaddr(A1ADDR), .portadatain(A1DATA), - .portawe(A1EN), + .portawe(A1EN_N), .portbaddr(B1ADDR), .portbdataout(B1DATA), .portbre(B1EN), |