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-rw-r--r--techlibs/intel_alm/common/alm_sim.v80
-rw-r--r--techlibs/intel_alm/common/bram_m10k.txt4
-rw-r--r--techlibs/intel_alm/common/bram_m10k_map.v31
-rw-r--r--techlibs/intel_alm/common/dff_sim.v55
-rw-r--r--techlibs/intel_alm/common/dsp_sim.v17
-rw-r--r--techlibs/intel_alm/common/megafunction_bb.v468
-rw-r--r--techlibs/intel_alm/common/mem_sim.v47
-rw-r--r--techlibs/intel_alm/common/quartus_rename.v51
8 files changed, 645 insertions, 108 deletions
diff --git a/techlibs/intel_alm/common/alm_sim.v b/techlibs/intel_alm/common/alm_sim.v
index 979c51132..906a95b0b 100644
--- a/techlibs/intel_alm/common/alm_sim.v
+++ b/techlibs/intel_alm/common/alm_sim.v
@@ -69,6 +69,14 @@
`default_nettype none
+// Cyclone V LUT output timings (picoseconds):
+//
+// CARRY A B C D E F G
+// COMBOUT - 605 583 510 512 - 97 400 (LUT6)
+// COMBOUT - 602 583 457 510 302 93 483 (LUT7)
+// SUMOUT 368 1342 1323 887 927 - 785 -
+// CARRYOUT 71 1082 1062 866 813 - 1198 -
+
(* abc9_lut=2, lib_whitebox *)
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
@@ -76,12 +84,12 @@ parameter [63:0] LUT = 64'h0000_0000_0000_0000;
`ifdef cyclonev
specify
- (A => Q) = 602;
- (B => Q) = 584;
+ (A => Q) = 605;
+ (B => Q) = 583;
(C => Q) = 510;
- (D => Q) = 510;
- (E => Q) = 339;
- (F => Q) = 94;
+ (D => Q) = 512;
+ (E => Q) = 400;
+ (F => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -107,11 +115,11 @@ parameter [31:0] LUT = 32'h0000_0000;
`ifdef cyclonev
specify
- (A => Q) = 584;
+ (A => Q) = 583;
(B => Q) = 510;
- (C => Q) = 510;
- (D => Q) = 339;
- (E => Q) = 94;
+ (C => Q) = 512;
+ (D => Q) = 400;
+ (E => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -137,9 +145,9 @@ parameter [15:0] LUT = 16'h0000;
`ifdef cyclonev
specify
(A => Q) = 510;
- (B => Q) = 510;
- (C => Q) = 339;
- (D => Q) = 94;
+ (B => Q) = 512;
+ (C => Q) = 400;
+ (D => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -164,8 +172,8 @@ parameter [7:0] LUT = 8'h00;
`ifdef cyclonev
specify
(A => Q) = 510;
- (B => Q) = 339;
- (C => Q) = 94;
+ (B => Q) = 400;
+ (C => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -188,8 +196,8 @@ parameter [3:0] LUT = 4'h0;
`ifdef cyclonev
specify
- (A => Q) = 339;
- (B => Q) = 94;
+ (A => Q) = 400;
+ (B => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -209,7 +217,7 @@ module MISTRAL_NOT(input A, output Q);
`ifdef cyclonev
specify
- (A => Q) = 94;
+ (A => Q) = 97;
endspecify
`endif
`ifdef cyclone10gx
@@ -230,31 +238,33 @@ parameter LUT1 = 16'h0000;
`ifdef cyclonev
specify
- (A => SO) = 1283;
- (B => SO) = 1167;
- (C => SO) = 866;
- (D0 => SO) = 756;
- (D1 => SO) = 756;
- (CI => SO) = 355;
- (A => CO) = 950;
- (B => CO) = 1039;
- (C => CO) = 820;
- (D0 => CO) = 1006;
- (D1 => CO) = 1006;
- (CI => CO) = 23;
+ (A => SO) = 1342;
+ (B => SO) = 1323;
+ (C => SO) = 927;
+ (D0 => SO) = 887;
+ (D1 => SO) = 785;
+ (CI => SO) = 368;
+
+ (A => CO) = 1082;
+ (B => CO) = 1062;
+ (C => CO) = 813;
+ (D0 => CO) = 866;
+ (D1 => CO) = 1198;
+ (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
endspecify
`endif
`ifdef cyclone10gx
specify
- (A => SO) = 644;
- (B => SO) = 477;
- (C => SO) = 416;
+ (A => SO) = 644;
+ (B => SO) = 477;
+ (C => SO) = 416;
(D0 => SO) = 380;
(D1 => SO) = 431;
(CI => SO) = 276;
- (A => CO) = 525;
- (B => CO) = 433;
- (C => CO) = 712;
+
+ (A => CO) = 525;
+ (B => CO) = 433;
+ (C => CO) = 712;
(D0 => CO) = 653;
(D1 => CO) = 593;
(CI => CO) = 16;
diff --git a/techlibs/intel_alm/common/bram_m10k.txt b/techlibs/intel_alm/common/bram_m10k.txt
index 837e3a330..e9355fe2c 100644
--- a/techlibs/intel_alm/common/bram_m10k.txt
+++ b/techlibs/intel_alm/common/bram_m10k.txt
@@ -1,4 +1,4 @@
-bram __MISTRAL_M10K_SDP
+bram MISTRAL_M10K
init 0 # TODO: Re-enable when I figure out how BRAM init works
abits 13 @D8192x1
dbits 1 @D8192x1
@@ -27,7 +27,7 @@ bram __MISTRAL_M10K_SDP
endbram
-match __MISTRAL_M10K_SDP
+match MISTRAL_M10K
min efficiency 5
make_transp
endmatch
diff --git a/techlibs/intel_alm/common/bram_m10k_map.v b/techlibs/intel_alm/common/bram_m10k_map.v
deleted file mode 100644
index 061463c3e..000000000
--- a/techlibs/intel_alm/common/bram_m10k_map.v
+++ /dev/null
@@ -1,31 +0,0 @@
-module __MISTRAL_M10K_SDP(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
-
-parameter CFG_ABITS = 10;
-parameter CFG_DBITS = 10;
-parameter CFG_ENABLE_A = 1;
-parameter CFG_ENABLE_B = 1;
-
-input CLK1;
-input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
-input [CFG_DBITS-1:0] A1DATA;
-output [CFG_DBITS-1:0] B1DATA;
-input [CFG_ENABLE_A-1:0] A1EN, B1EN;
-
-altsyncram #(
- .operation_mode("dual_port"),
- .ram_block_type("m10k"),
- .widthad_a(CFG_ABITS),
- .width_a(CFG_DBITS),
- .widthad_b(CFG_ABITS),
- .width_b(CFG_DBITS),
-) _TECHMAP_REPLACE_ (
- .address_a(A1ADDR),
- .data_a(A1DATA),
- .wren_a(A1EN),
- .address_b(B1ADDR),
- .q_b(B1DATA),
- .clock0(CLK1),
- .clock1(CLK1)
-);
-
-endmodule
diff --git a/techlibs/intel_alm/common/dff_sim.v b/techlibs/intel_alm/common/dff_sim.v
index 9ff8f9f67..d2cff0adb 100644
--- a/techlibs/intel_alm/common/dff_sim.v
+++ b/techlibs/intel_alm/common/dff_sim.v
@@ -54,43 +54,44 @@
//
// Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.
-`ifdef cyclonev
-`define SYNCPATH 262
-`define SYNCSETUP 522
-`define COMBPATH 0
-`endif
-`ifdef cyclone10gx
-`define SYNCPATH 219
-`define SYNCSETUP 268
-`define COMBPATH 0
-`endif
-
-// fallback for when a family isn't detected (e.g. when techmapping for equivalence)
-`ifndef SYNCPATH
-`define SYNCPATH 0
-`define SYNCSETUP 0
-`define COMBPATH 0
-`endif
-
(* abc9_box, lib_whitebox *)
module MISTRAL_FF(
input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
output reg Q
);
+`ifdef cyclonev
specify
- if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = `SYNCPATH;
- if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = `SYNCPATH;
- if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = `SYNCPATH;
+ if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
+ if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
+ if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618;
- $setup(DATAIN, posedge CLK, `SYNCSETUP);
- $setup(ENA, posedge CLK, `SYNCSETUP);
- $setup(SCLR, posedge CLK, `SYNCSETUP);
- $setup(SLOAD, posedge CLK, `SYNCSETUP);
- $setup(SDATA, posedge CLK, `SYNCSETUP);
+ $setup(DATAIN, posedge CLK, /* -196 */ 0);
+ $setup(ENA, posedge CLK, /* -196 */ 0);
+ $setup(SCLR, posedge CLK, /* -196 */ 0);
+ $setup(SLOAD, posedge CLK, /* -196 */ 0);
+ $setup(SDATA, posedge CLK, /* -196 */ 0);
- if (ACLR === 1'b0) (ACLR => Q) = `COMBPATH;
+ if (ACLR === 1'b0) (ACLR => Q) = 282;
endspecify
+`endif
+`ifdef cyclone10gx
+specify
+ // TODO (long-term): investigate these numbers.
+ // It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
+ if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
+ if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
+ if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
+
+ $setup(DATAIN, posedge CLK, 268);
+ $setup(ENA, posedge CLK, 268);
+ $setup(SCLR, posedge CLK, 268);
+ $setup(SLOAD, posedge CLK, 268);
+ $setup(SDATA, posedge CLK, 268);
+
+ if (ACLR === 1'b0) (ACLR => Q) = 0;
+endspecify
+`endif
initial begin
// Altera flops initialise to zero.
diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v
index 5dc4c02de..45fdebb3f 100644
--- a/techlibs/intel_alm/common/dsp_sim.v
+++ b/techlibs/intel_alm/common/dsp_sim.v
@@ -1,9 +1,10 @@
(* abc9_box *)
-module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y);
+module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);
+// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
- (A *> Y) = 4057;
- (B *> Y) = 4057;
+ (A *> Y) = 3732;
+ (B *> Y) = 3928;
endspecify
assign Y = $signed(A) * $signed(B);
@@ -13,9 +14,10 @@ endmodule
(* abc9_box *)
module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
+// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
- (A *> Y) = 4057;
- (B *> Y) = 4057;
+ (A *> Y) = 3180;
+ (B *> Y) = 3982;
endspecify
assign Y = $signed(A) * $signed(B);
@@ -25,9 +27,10 @@ endmodule
(* abc9_box *)
module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
+// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
- (A *> Y) = 4057;
- (B *> Y) = 4057;
+ (A *> Y) = 2818;
+ (B *> Y) = 3051;
endspecify
assign Y = $signed(A) * $signed(B);
diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v
index b5a3d8892..530e44054 100644
--- a/techlibs/intel_alm/common/megafunction_bb.v
+++ b/techlibs/intel_alm/common/megafunction_bb.v
@@ -2,6 +2,306 @@
`default_nettype none
(* blackbox *)
+module altera_pll
+#(
+ parameter reference_clock_frequency = "0 ps",
+ parameter fractional_vco_multiplier = "false",
+ parameter pll_type = "General",
+ parameter pll_subtype = "General",
+ parameter number_of_clocks = 1,
+ parameter operation_mode = "internal feedback",
+ parameter deserialization_factor = 4,
+ parameter data_rate = 0,
+
+ parameter sim_additional_refclk_cycles_to_lock = 0,
+ parameter output_clock_frequency0 = "0 ps",
+ parameter phase_shift0 = "0 ps",
+ parameter duty_cycle0 = 50,
+
+ parameter output_clock_frequency1 = "0 ps",
+ parameter phase_shift1 = "0 ps",
+ parameter duty_cycle1 = 50,
+
+ parameter output_clock_frequency2 = "0 ps",
+ parameter phase_shift2 = "0 ps",
+ parameter duty_cycle2 = 50,
+
+ parameter output_clock_frequency3 = "0 ps",
+ parameter phase_shift3 = "0 ps",
+ parameter duty_cycle3 = 50,
+
+ parameter output_clock_frequency4 = "0 ps",
+ parameter phase_shift4 = "0 ps",
+ parameter duty_cycle4 = 50,
+
+ parameter output_clock_frequency5 = "0 ps",
+ parameter phase_shift5 = "0 ps",
+ parameter duty_cycle5 = 50,
+
+ parameter output_clock_frequency6 = "0 ps",
+ parameter phase_shift6 = "0 ps",
+ parameter duty_cycle6 = 50,
+
+ parameter output_clock_frequency7 = "0 ps",
+ parameter phase_shift7 = "0 ps",
+ parameter duty_cycle7 = 50,
+
+ parameter output_clock_frequency8 = "0 ps",
+ parameter phase_shift8 = "0 ps",
+ parameter duty_cycle8 = 50,
+
+ parameter output_clock_frequency9 = "0 ps",
+ parameter phase_shift9 = "0 ps",
+ parameter duty_cycle9 = 50,
+
+
+ parameter output_clock_frequency10 = "0 ps",
+ parameter phase_shift10 = "0 ps",
+ parameter duty_cycle10 = 50,
+
+ parameter output_clock_frequency11 = "0 ps",
+ parameter phase_shift11 = "0 ps",
+ parameter duty_cycle11 = 50,
+
+ parameter output_clock_frequency12 = "0 ps",
+ parameter phase_shift12 = "0 ps",
+ parameter duty_cycle12 = 50,
+
+ parameter output_clock_frequency13 = "0 ps",
+ parameter phase_shift13 = "0 ps",
+ parameter duty_cycle13 = 50,
+
+ parameter output_clock_frequency14 = "0 ps",
+ parameter phase_shift14 = "0 ps",
+ parameter duty_cycle14 = 50,
+
+ parameter output_clock_frequency15 = "0 ps",
+ parameter phase_shift15 = "0 ps",
+ parameter duty_cycle15 = 50,
+
+ parameter output_clock_frequency16 = "0 ps",
+ parameter phase_shift16 = "0 ps",
+ parameter duty_cycle16 = 50,
+
+ parameter output_clock_frequency17 = "0 ps",
+ parameter phase_shift17 = "0 ps",
+ parameter duty_cycle17 = 50,
+
+ parameter clock_name_0 = "",
+ parameter clock_name_1 = "",
+ parameter clock_name_2 = "",
+ parameter clock_name_3 = "",
+ parameter clock_name_4 = "",
+ parameter clock_name_5 = "",
+ parameter clock_name_6 = "",
+ parameter clock_name_7 = "",
+ parameter clock_name_8 = "",
+
+ parameter clock_name_global_0 = "false",
+ parameter clock_name_global_1 = "false",
+ parameter clock_name_global_2 = "false",
+ parameter clock_name_global_3 = "false",
+ parameter clock_name_global_4 = "false",
+ parameter clock_name_global_5 = "false",
+ parameter clock_name_global_6 = "false",
+ parameter clock_name_global_7 = "false",
+ parameter clock_name_global_8 = "false",
+
+ parameter m_cnt_hi_div = 1,
+ parameter m_cnt_lo_div = 1,
+ parameter m_cnt_bypass_en = "false",
+ parameter m_cnt_odd_div_duty_en = "false",
+ parameter n_cnt_hi_div = 1,
+ parameter n_cnt_lo_div = 1,
+ parameter n_cnt_bypass_en = "false",
+ parameter n_cnt_odd_div_duty_en = "false",
+ parameter c_cnt_hi_div0 = 1,
+ parameter c_cnt_lo_div0 = 1,
+ parameter c_cnt_bypass_en0 = "false",
+ parameter c_cnt_in_src0 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en0 = "false",
+ parameter c_cnt_prst0 = 1,
+ parameter c_cnt_ph_mux_prst0 = 0,
+ parameter c_cnt_hi_div1 = 1,
+ parameter c_cnt_lo_div1 = 1,
+ parameter c_cnt_bypass_en1 = "false",
+ parameter c_cnt_in_src1 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en1 = "false",
+ parameter c_cnt_prst1 = 1,
+ parameter c_cnt_ph_mux_prst1 = 0,
+ parameter c_cnt_hi_div2 = 1,
+ parameter c_cnt_lo_div2 = 1,
+ parameter c_cnt_bypass_en2 = "false",
+ parameter c_cnt_in_src2 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en2 = "false",
+ parameter c_cnt_prst2 = 1,
+ parameter c_cnt_ph_mux_prst2 = 0,
+ parameter c_cnt_hi_div3 = 1,
+ parameter c_cnt_lo_div3 = 1,
+ parameter c_cnt_bypass_en3 = "false",
+ parameter c_cnt_in_src3 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en3 = "false",
+ parameter c_cnt_prst3 = 1,
+ parameter c_cnt_ph_mux_prst3 = 0,
+ parameter c_cnt_hi_div4 = 1,
+ parameter c_cnt_lo_div4 = 1,
+ parameter c_cnt_bypass_en4 = "false",
+ parameter c_cnt_in_src4 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en4 = "false",
+ parameter c_cnt_prst4 = 1,
+ parameter c_cnt_ph_mux_prst4 = 0,
+ parameter c_cnt_hi_div5 = 1,
+ parameter c_cnt_lo_div5 = 1,
+ parameter c_cnt_bypass_en5 = "false",
+ parameter c_cnt_in_src5 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en5 = "false",
+ parameter c_cnt_prst5 = 1,
+ parameter c_cnt_ph_mux_prst5 = 0,
+ parameter c_cnt_hi_div6 = 1,
+ parameter c_cnt_lo_div6 = 1,
+ parameter c_cnt_bypass_en6 = "false",
+ parameter c_cnt_in_src6 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en6 = "false",
+ parameter c_cnt_prst6 = 1,
+ parameter c_cnt_ph_mux_prst6 = 0,
+ parameter c_cnt_hi_div7 = 1,
+ parameter c_cnt_lo_div7 = 1,
+ parameter c_cnt_bypass_en7 = "false",
+ parameter c_cnt_in_src7 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en7 = "false",
+ parameter c_cnt_prst7 = 1,
+ parameter c_cnt_ph_mux_prst7 = 0,
+ parameter c_cnt_hi_div8 = 1,
+ parameter c_cnt_lo_div8 = 1,
+ parameter c_cnt_bypass_en8 = "false",
+ parameter c_cnt_in_src8 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en8 = "false",
+ parameter c_cnt_prst8 = 1,
+ parameter c_cnt_ph_mux_prst8 = 0,
+ parameter c_cnt_hi_div9 = 1,
+ parameter c_cnt_lo_div9 = 1,
+ parameter c_cnt_bypass_en9 = "false",
+ parameter c_cnt_in_src9 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en9 = "false",
+ parameter c_cnt_prst9 = 1,
+ parameter c_cnt_ph_mux_prst9 = 0,
+ parameter c_cnt_hi_div10 = 1,
+ parameter c_cnt_lo_div10 = 1,
+ parameter c_cnt_bypass_en10 = "false",
+ parameter c_cnt_in_src10 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en10 = "false",
+ parameter c_cnt_prst10 = 1,
+ parameter c_cnt_ph_mux_prst10 = 0,
+ parameter c_cnt_hi_div11 = 1,
+ parameter c_cnt_lo_div11 = 1,
+ parameter c_cnt_bypass_en11 = "false",
+ parameter c_cnt_in_src11 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en11 = "false",
+ parameter c_cnt_prst11 = 1,
+ parameter c_cnt_ph_mux_prst11 = 0,
+ parameter c_cnt_hi_div12 = 1,
+ parameter c_cnt_lo_div12 = 1,
+ parameter c_cnt_bypass_en12 = "false",
+ parameter c_cnt_in_src12 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en12 = "false",
+ parameter c_cnt_prst12 = 1,
+ parameter c_cnt_ph_mux_prst12 = 0,
+ parameter c_cnt_hi_div13 = 1,
+ parameter c_cnt_lo_div13 = 1,
+ parameter c_cnt_bypass_en13 = "false",
+ parameter c_cnt_in_src13 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en13 = "false",
+ parameter c_cnt_prst13 = 1,
+ parameter c_cnt_ph_mux_prst13 = 0,
+ parameter c_cnt_hi_div14 = 1,
+ parameter c_cnt_lo_div14 = 1,
+ parameter c_cnt_bypass_en14 = "false",
+ parameter c_cnt_in_src14 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en14 = "false",
+ parameter c_cnt_prst14 = 1,
+ parameter c_cnt_ph_mux_prst14 = 0,
+ parameter c_cnt_hi_div15 = 1,
+ parameter c_cnt_lo_div15 = 1,
+ parameter c_cnt_bypass_en15 = "false",
+ parameter c_cnt_in_src15 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en15 = "false",
+ parameter c_cnt_prst15 = 1,
+ parameter c_cnt_ph_mux_prst15 = 0,
+ parameter c_cnt_hi_div16 = 1,
+ parameter c_cnt_lo_div16 = 1,
+ parameter c_cnt_bypass_en16 = "false",
+ parameter c_cnt_in_src16 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en16 = "false",
+ parameter c_cnt_prst16 = 1,
+ parameter c_cnt_ph_mux_prst16 = 0,
+ parameter c_cnt_hi_div17 = 1,
+ parameter c_cnt_lo_div17 = 1,
+ parameter c_cnt_bypass_en17 = "false",
+ parameter c_cnt_in_src17 = "ph_mux_clk",
+ parameter c_cnt_odd_div_duty_en17 = "false",
+ parameter c_cnt_prst17 = 1,
+ parameter c_cnt_ph_mux_prst17 = 0,
+ parameter pll_vco_div = 1,
+ parameter pll_slf_rst = "false",
+ parameter pll_bw_sel = "low",
+ parameter pll_output_clk_frequency = "0 MHz",
+ parameter pll_cp_current = 0,
+ parameter pll_bwctrl = 0,
+ parameter pll_fractional_division = 1,
+ parameter pll_fractional_cout = 24,
+ parameter pll_dsm_out_sel = "1st_order",
+ parameter mimic_fbclk_type = "gclk",
+ parameter pll_fbclk_mux_1 = "glb",
+ parameter pll_fbclk_mux_2 = "fb_1",
+ parameter pll_m_cnt_in_src = "ph_mux_clk",
+ parameter pll_vcoph_div = 1,
+ parameter refclk1_frequency = "0 MHz",
+ parameter pll_clkin_0_src = "clk_0",
+ parameter pll_clkin_1_src = "clk_0",
+ parameter pll_clk_loss_sw_en = "false",
+ parameter pll_auto_clk_sw_en = "false",
+ parameter pll_manu_clk_sw_en = "false",
+ parameter pll_clk_sw_dly = 0,
+ parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
+ parameter pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss"
+) (
+ //input
+ input refclk,
+ input refclk1,
+ input fbclk,
+ input rst,
+ input phase_en,
+ input updn,
+ input [2:0] num_phase_shifts,
+ input scanclk,
+ input [4:0] cntsel,
+ input [63:0] reconfig_to_pll,
+ input extswitch,
+ input adjpllin,
+ input cclk,
+
+ //output
+ output [ number_of_clocks -1 : 0] outclk,
+ output fboutclk,
+ output locked,
+ output phase_done,
+ output [63:0] reconfig_from_pll,
+ output activeclk,
+ output [1:0] clkbad,
+ output [7:0] phout,
+ output [1:0] lvds_clk,
+ output [1:0] loaden,
+ output [1:0] extclk_out,
+ output [ number_of_clocks -1 : 0] cascade_out,
+
+ //inout
+ inout zdbfbclk
+);
+
+endmodule
+
+
+(* blackbox *)
module altera_std_synchronizer(clk, din, dout, reset_n);
parameter depth = 2;
@@ -14,6 +314,137 @@ output dout;
endmodule
(* blackbox *)
+module altddio_in (
+ datain, // required port, DDR input data
+ inclock, // required port, input reference clock to sample data by
+ inclocken, // enable data clock
+ aset, // asynchronous set
+ aclr, // asynchronous clear
+ sset, // synchronous set
+ sclr, // synchronous clear
+ dataout_h, // data sampled at the rising edge of inclock
+ dataout_l // data sampled at the falling edge of inclock
+);
+
+parameter width = 1;
+parameter power_up_high = "OFF";
+parameter invert_input_clocks = "OFF";
+parameter intended_device_family = "Stratix";
+parameter lpm_type = "altddio_in";
+parameter lpm_hint = "UNUSED";
+
+input [width-1:0] datain;
+input inclock;
+input inclocken;
+input aset;
+input aclr;
+input sset;
+input sclr;
+
+output [width-1:0] dataout_h;
+output [width-1:0] dataout_l;
+
+endmodule
+
+
+(* blackbox *)
+module altddio_out (
+ datain_h,
+ datain_l,
+ outclock,
+ outclocken,
+ aset,
+ aclr,
+ sset,
+ sclr,
+ oe,
+ dataout,
+ oe_out
+);
+
+parameter width = 1;
+parameter power_up_high = "OFF";
+parameter oe_reg = "UNUSED";
+parameter extend_oe_disable = "UNUSED";
+parameter intended_device_family = "Stratix";
+parameter invert_output = "OFF";
+parameter lpm_type = "altddio_out";
+parameter lpm_hint = "UNUSED";
+
+input [width-1:0] datain_h;
+input [width-1:0] datain_l;
+input outclock;
+input outclocken;
+input aset;
+input aclr;
+input sset;
+input sclr;
+input oe;
+
+output [width-1:0] dataout;
+output [width-1:0] oe_out;
+
+endmodule
+
+
+(* blackbox *)
+module altddio_bidir (
+ datain_h,
+ datain_l,
+ inclock,
+ inclocken,
+ outclock,
+ outclocken,
+ aset,
+ aclr,
+ sset,
+ sclr,
+ oe,
+ dataout_h,
+ dataout_l,
+ combout,
+ oe_out,
+ dqsundelayedout,
+ padio
+);
+
+// GLOBAL PARAMETER DECLARATION
+parameter width = 1; // required parameter
+parameter power_up_high = "OFF";
+parameter oe_reg = "UNUSED";
+parameter extend_oe_disable = "UNUSED";
+parameter implement_input_in_lcell = "UNUSED";
+parameter invert_output = "OFF";
+parameter intended_device_family = "Stratix";
+parameter lpm_type = "altddio_bidir";
+parameter lpm_hint = "UNUSED";
+
+// INPUT PORT DECLARATION
+input [width-1:0] datain_h;
+input [width-1:0] datain_l;
+input inclock;
+input inclocken;
+input outclock;
+input outclocken;
+input aset;
+input aclr;
+input sset;
+input sclr;
+input oe;
+
+// OUTPUT PORT DECLARATION
+output [width-1:0] dataout_h;
+output [width-1:0] dataout_l;
+output [width-1:0] combout;
+output [width-1:0] oe_out;
+output [width-1:0] dqsundelayedout;
+// BIDIRECTIONAL PORT DECLARATION
+inout [width-1:0] padio;
+
+endmodule
+
+
+(* blackbox *)
module altiobuf_in(datain, dataout);
parameter enable_bus_hold = "FALSE";
@@ -156,4 +587,39 @@ input [ax_width-1:0] ax;
input [ay_scan_in_width-1:0] ay;
output [result_a_width-1:0] resulta;
-endmodule \ No newline at end of file
+endmodule
+
+(* blackbox *)
+module cyclonev_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0);
+
+parameter operation_mode = "dual_port";
+parameter logical_ram_name = "";
+parameter port_a_address_width = 10;
+parameter port_a_data_width = 10;
+parameter port_a_logical_ram_depth = 1024;
+parameter port_a_logical_ram_width = 10;
+parameter port_a_first_address = 0;
+parameter port_a_last_address = 1023;
+parameter port_a_first_bit_number = 0;
+parameter port_b_address_width = 10;
+parameter port_b_data_width = 10;
+parameter port_b_logical_ram_depth = 1024;
+parameter port_b_logical_ram_width = 10;
+parameter port_b_first_address = 0;
+parameter port_b_last_address = 1023;
+parameter port_b_first_bit_number = 0;
+parameter port_b_address_clock = "clock0";
+parameter port_b_read_enable_clock = "clock0";
+parameter mem_init0 = "";
+parameter mem_init1 = "";
+parameter mem_init2 = "";
+parameter mem_init3 = "";
+parameter mem_init4 = "";
+
+input [port_a_address_width-1:0] portaaddr;
+input [port_b_address_width-1:0] portbaddr;
+input [port_a_data_width-1:0] portadatain;
+output [port_b_data_width-1:0] portbdataout;
+input clk0, portawe, portbre;
+
+endmodule
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v
index f6f9ecb02..e09aafaa2 100644
--- a/techlibs/intel_alm/common/mem_sim.v
+++ b/techlibs/intel_alm/common/mem_sim.v
@@ -54,12 +54,17 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
reg [31:0] mem = 32'b0;
-// TODO
+// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
specify
- $setup(A1ADDR, posedge CLK1, 0);
- $setup(A1DATA, posedge CLK1, 0);
+ $setup(A1ADDR, posedge CLK1, 86);
+ $setup(A1DATA, posedge CLK1, 86);
+ $setup(A1EN, posedge CLK1, 86);
- (B1ADDR *> B1DATA) = 0;
+ (B1ADDR[0] => B1DATA) = 487;
+ (B1ADDR[1] => B1DATA) = 475;
+ (B1ADDR[2] => B1DATA) = 382;
+ (B1ADDR[3] => B1DATA) = 284;
+ (B1ADDR[4] => B1DATA) = 96;
endspecify
always @(posedge CLK1)
@@ -68,3 +73,37 @@ always @(posedge CLK1)
assign B1DATA = mem[B1ADDR];
endmodule
+
+// The M10K
+// --------
+// TODO
+
+module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+
+parameter CFG_ABITS = 10;
+parameter CFG_DBITS = 10;
+
+input CLK1;
+input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
+input [CFG_DBITS-1:0] A1DATA;
+input A1EN, B1EN;
+output reg [CFG_DBITS-1:0] B1DATA;
+
+reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
+
+specify
+ $setup(A1ADDR, posedge CLK1, 0);
+ $setup(A1DATA, posedge CLK1, 0);
+
+ if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0;
+endspecify
+
+always @(posedge CLK1) begin
+ if (A1EN)
+ mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
+
+ if (B1EN)
+ B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];
+end
+
+endmodule
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
index 46ef2aa0d..9bc532ca2 100644
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ b/techlibs/intel_alm/common/quartus_rename.v
@@ -88,6 +88,8 @@ endmodule
module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
+parameter _TECHMAP_CELLNAME_ = "";
+
// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
// which takes in a hexadecimal string that could be used to initialise RAM.
// In the vendor simulation models, this appears to work fine, but Quartus,
@@ -99,7 +101,7 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
// or an undocumented way to get Quartus to initialise from mem_init0 is found.
`MLAB #(
- .logical_ram_name("MISTRAL_MLAB"),
+ .logical_ram_name(_TECHMAP_CELLNAME_),
.logical_ram_depth(32),
.logical_ram_width(1),
.mixed_port_feed_through_mode("Dont Care"),
@@ -123,6 +125,53 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
endmodule
+module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
+
+parameter CFG_ABITS = 10;
+parameter CFG_DBITS = 10;
+
+parameter _TECHMAP_CELLNAME_ = "";
+
+input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
+input [CFG_DBITS-1:0] A1DATA;
+input CLK1, A1EN, B1EN;
+output [CFG_DBITS-1:0] B1DATA;
+
+// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
+// you initialise the RAM cell via hex literals. If they were implemented.
+
+cyclonev_ram_block #(
+ .operation_mode("dual_port"),
+ .logical_ram_name(_TECHMAP_CELLNAME_),
+ .port_a_address_width(CFG_ABITS),
+ .port_a_data_width(CFG_DBITS),
+ .port_a_logical_ram_depth(2**CFG_ABITS),
+ .port_a_logical_ram_width(CFG_DBITS),
+ .port_a_first_address(0),
+ .port_a_last_address(2**CFG_ABITS - 1),
+ .port_a_first_bit_number(0),
+ .port_b_address_width(CFG_ABITS),
+ .port_b_data_width(CFG_DBITS),
+ .port_b_logical_ram_depth(2**CFG_ABITS),
+ .port_b_logical_ram_width(CFG_DBITS),
+ .port_b_first_address(0),
+ .port_b_last_address(2**CFG_ABITS - 1),
+ .port_b_first_bit_number(0),
+ .port_b_address_clock("clock0"),
+ .port_b_read_enable_clock("clock0")
+) _TECHMAP_REPLACE_ (
+ .portaaddr(A1ADDR),
+ .portadatain(A1DATA),
+ .portawe(A1EN),
+ .portbaddr(B1ADDR),
+ .portbdataout(B1DATA),
+ .portbre(B1EN),
+ .clk0(CLK1)
+);
+
+endmodule
+
+
module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
`MAC #(.ax_width(27), .ay_scan_in_width(27), .result_a_width(54), .operation_mode("M27x27")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y));
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