diff options
Diffstat (limited to 'techlibs/intel_alm/synth_intel_alm.cc')
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index bf9e746b8..fabfc9003 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN struct SynthIntelALMPass : public ScriptPass { SynthIntelALMPass() : ScriptPass("synth_intel_alm", "synthesis for ALM-based Intel (Altera) FPGAs.") {} - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -74,7 +74,7 @@ struct SynthIntelALMPass : public ScriptPass { string top_opt, family_opt, bram_type, vout_file; bool flatten, quartus, nolutram, nobram; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; family_opt = "cyclonev"; @@ -86,7 +86,7 @@ struct SynthIntelALMPass : public ScriptPass { nobram = false; } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -153,7 +153,7 @@ struct SynthIntelALMPass : public ScriptPass { log_pop(); } - void script() YS_OVERRIDE + void script() override { if (help_mode) { family_opt = "<family>"; @@ -199,7 +199,7 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_ffs")) { - run("dff2dffe -direct-match $_DFF_*"); + run("dff2dffe"); // As mentioned in common/dff_sim.v, Intel flops power up to zero, // so use `zinit` to add inverters where needed. run("zinit"); @@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_luts")) { - run("read_verilog -icells -specify -lib +/abc9_model.v"); run("abc9 -maxlut 6 -W 200"); run("techmap -map +/intel_alm/common/alm_map.v"); run("opt -fast"); |