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-rw-r--r--techlibs/machxo2/cells_sim.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
index 22b4fcf3c..8db73c50c 100644
--- a/techlibs/machxo2/cells_sim.v
+++ b/techlibs/machxo2/cells_sim.v
@@ -42,7 +42,7 @@ module FACADE_FF #(
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
- assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+ wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
generate
if (SRMODE == "ASYNC") begin