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-rw-r--r--techlibs/machxo2/Makefile.inc5
-rw-r--r--techlibs/machxo2/cells_map.v34
-rw-r--r--techlibs/machxo2/cells_sim.v212
-rw-r--r--techlibs/machxo2/synth_machxo2.cc249
4 files changed, 500 insertions, 0 deletions
diff --git a/techlibs/machxo2/Makefile.inc b/techlibs/machxo2/Makefile.inc
new file mode 100644
index 000000000..6f6f6ce94
--- /dev/null
+++ b/techlibs/machxo2/Makefile.inc
@@ -0,0 +1,5 @@
+
+OBJS += techlibs/machxo2/synth_machxo2.o
+
+$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v))
+$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v))
diff --git a/techlibs/machxo2/cells_map.v b/techlibs/machxo2/cells_map.v
new file mode 100644
index 000000000..9c370f246
--- /dev/null
+++ b/techlibs/machxo2/cells_map.v
@@ -0,0 +1,34 @@
+module \$lut (A, Y);
+ parameter WIDTH = 0;
+ parameter LUT = 0;
+ input [WIDTH-1:0] A;
+ output Y;
+
+ localparam rep = 1<<(4-WIDTH);
+ wire [3:0] I;
+
+ generate
+ if(WIDTH == 1) begin
+ assign I = {1'b0, 1'b0, 1'b0, A[0]};
+ end else if(WIDTH == 2) begin
+ assign I = {1'b0, 1'b0, A[1], A[0]};
+ end else if(WIDTH == 3) begin
+ assign I = {1'b0, A[2], A[1], A[0]};
+ end else if(WIDTH == 4) begin
+ assign I = {A[3], A[2], A[1], A[0]};
+ end else begin
+ wire _TECHMAP_FAIL_ = 1;
+ end
+ endgenerate
+
+ LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y));
+endmodule
+
+// DFFs
+module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+// IO- "$__" cells for the iopadmap pass.
+module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(1'b0)); endmodule
+module \$__FACADE_INPAD (input I, output O); FACADE_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.PAD(I), .O(O)); endmodule
+module \$__FACADE_TOUTPAD (input I, T, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(T)); endmodule
+module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(T)); endmodule
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
new file mode 100644
index 000000000..dc68a3127
--- /dev/null
+++ b/techlibs/machxo2/cells_sim.v
@@ -0,0 +1,212 @@
+module LUT4 #(
+ parameter [15:0] INIT = 0
+) (
+ input A, B, C, D,
+ output Z
+);
+ // This form of LUT propagates as few x's as possible.
+ wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
+ wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
+ wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
+ assign Z = A ? s1[1] : s1[0];
+endmodule
+
+module FACADE_FF #(
+ parameter GSR = "ENABLED",
+ parameter CEMUX = "1",
+ parameter CLKMUX = "0",
+ parameter LSRMUX = "LSR",
+ parameter LSRONMUX = "LSRMUX",
+ parameter SRMODE = "LSR_OVER_CE",
+ parameter REGSET = "SET",
+ parameter REGMODE = "FF"
+) (
+ input CLK, DI, LSR, CE,
+ output reg Q
+);
+
+ wire muxce;
+ generate
+ case (CEMUX)
+ "1": assign muxce = 1'b1;
+ "0": assign muxce = 1'b0;
+ "INV": assign muxce = ~CE;
+ default: assign muxce = CE;
+ endcase
+ endgenerate
+
+ wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
+ wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0;
+ wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
+ wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+
+ initial Q = srval;
+
+ generate
+ if (REGMODE == "FF") begin
+ if (SRMODE == "ASYNC") begin
+ always @(posedge muxclk, posedge muxlsron)
+ if (muxlsron)
+ Q <= srval;
+ else if (muxce)
+ Q <= DI;
+ end else begin
+ always @(posedge muxclk)
+ if (muxlsron)
+ Q <= srval;
+ else if (muxce)
+ Q <= DI;
+ end
+ end else if (REGMODE == "LATCH") begin
+ ERROR_UNSUPPORTED_FF_MODE error();
+ end else begin
+ ERROR_UNKNOWN_FF_MODE error();
+ end
+ endgenerate
+endmodule
+
+/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */
+module PFUMX (input ALUT, BLUT, C0, output Z);
+ assign Z = C0 ? ALUT : BLUT;
+endmodule
+
+/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */
+module L6MUX21 (input D0, D1, SD, output Z);
+ assign Z = SD ? D1 : D0;
+endmodule
+
+/* For consistency, input order matches TRELLIS_SLICE even though the BELs in
+prjtrellis were filled in clockwise order from bottom left. */
+module FACADE_SLICE #(
+ parameter MODE = "LOGIC",
+ parameter GSR = "ENABLED",
+ parameter SRMODE = "LSR_OVER_CE",
+ parameter CEMUX = "1",
+ parameter CLKMUX = "0",
+ parameter LSRMUX = "LSR",
+ parameter LSRONMUX = "LSRMUX",
+ parameter LUT0_INITVAL = 16'hFFFF,
+ parameter LUT1_INITVAL = 16'hFFFF,
+ parameter REGMODE = "FF",
+ parameter REG0_SD = "1",
+ parameter REG1_SD = "1",
+ parameter REG0_REGSET = "SET",
+ parameter REG1_REGSET = "SET",
+ parameter CCU2_INJECT1_0 = "YES",
+ parameter CCU2_INJECT1_1 = "YES",
+ parameter WREMUX = "INV"
+) (
+ input A0, B0, C0, D0,
+ input A1, B1, C1, D1,
+ input M0, M1,
+ input FCI, FXA, FXB,
+
+ input CLK, LSR, CE,
+ input DI0, DI1,
+
+ input WD0, WD1,
+ input WAD0, WAD1, WAD2, WAD3,
+ input WRE, WCK,
+
+ output F0, Q0,
+ output F1, Q1,
+ output FCO, OFX0, OFX1,
+
+ output WDO0, WDO1, WDO2, WDO3,
+ output WADO0, WADO1, WADO2, WADO3
+);
+
+ generate
+ if (MODE == "LOGIC") begin
+ L6MUX21 FXMUX (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
+
+ wire k0;
+ wire k1;
+ PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX0));
+
+ LUT4 #(.INIT(LUT0_INITVAL)) LUT_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k0));
+ LUT4 #(.INIT(LUT1_INITVAL)) LUT_1 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k1));
+
+ assign F0 = k0;
+ assign F1 = k1;
+ end else if (MODE == "CCU2") begin
+ ERROR_UNSUPPORTED_SLICE_MODE error();
+ end else if (MODE == "DPRAM") begin
+ ERROR_UNSUPPORTED_SLICE_MODE error();
+ end else begin
+ ERROR_UNKNOWN_SLICE_MODE error();
+ end
+ endgenerate
+
+ /* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F
+ outputs (in other words, feeds back into FACADE_SLICE). */
+ wire di0 = (REG0_SD == "1") ? DI0 : M0;
+ wire di1 = (REG1_SD == "1") ? DI1 : M1;
+
+ FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
+ .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET),
+ .REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0));
+ FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
+ .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET),
+ .REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1));
+endmodule
+
+module FACADE_IO #(
+ parameter DIR = "INPUT"
+) (
+ inout PAD,
+ input I, T,
+ output O
+);
+ generate
+ if (DIR == "INPUT") begin
+ assign O = PAD;
+ end else if (DIR == "OUTPUT") begin
+ assign PAD = T ? 1'bz : I;
+ end else if (DIR == "BIDIR") begin
+ assign PAD = T ? 1'bz : I;
+ assign O = PAD;
+ end else begin
+ ERROR_UNKNOWN_IO_MODE error();
+ end
+ endgenerate
+endmodule
+
+(* blackbox *)
+module OSCH #(
+ parameter NOM_FREQ = "2.08"
+) (
+ input STDBY,
+ output OSC,
+ output SEDSTDBY
+);
+endmodule
+
+(* blackbox *)
+module DCCA (
+ input CLKI,
+ input CE,
+ output CLKO
+);
+endmodule
+
+(* blackbox *)
+module DCMA (
+ input CLK0,
+ input CLK1,
+ input SEL,
+ output DCMOUT
+);
+endmodule
+
+// IO- "$__" cells for the iopadmap pass. These are temporary cells not meant
+// to be instantiated by the end user. They are required in this file for
+// attrmvcp to work.
+(* blackbox *)
+module \$__FACADE_OUTPAD (input I, output O); endmodule
+(* blackbox *)
+module \$__FACADE_INPAD (input I, output O); endmodule
+(* blackbox *)
+module \$__FACADE_TOUTPAD (input I, T, output O); endmodule
+(* blackbox *)
+module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); endmodule
diff --git a/techlibs/machxo2/synth_machxo2.cc b/techlibs/machxo2/synth_machxo2.cc
new file mode 100644
index 000000000..e86ec5aaf
--- /dev/null
+++ b/techlibs/machxo2/synth_machxo2.cc
@@ -0,0 +1,249 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 William D. Jones <wjones@wdj-consulting.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthMachXO2Pass : public ScriptPass
+{
+ SynthMachXO2Pass() : ScriptPass("synth_machxo2", "synthesis for MachXO2 FPGAs. This work is experimental.") { }
+
+ void help() override
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" synth_machxo2 [options]\n");
+ log("\n");
+ log("This command runs synthesis for MachXO2 FPGAs.\n");
+ log("\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module\n");
+ log("\n");
+ log(" -blif <file>\n");
+ log(" write the design to the specified BLIF file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -edif <file>\n");
+ log(" write the design to the specified EDIF file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -json <file>\n");
+ log(" write the design to the specified JSON file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -run <from_label>:<to_label>\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
+ log(" -noflatten\n");
+ log(" do not flatten design before synthesis\n");
+ log("\n");
+ log(" -noiopad\n");
+ log(" do not insert IO buffers\n");
+ log("\n");
+ log(" -vpr\n");
+ log(" generate an output netlist (and BLIF file) suitable for VPR\n");
+ log(" (this feature is experimental and incomplete)\n");
+ log("\n");
+ log("\n");
+ log("The following commands are executed by this synthesis command:\n");
+ help_script();
+ log("\n");
+ }
+
+ string top_opt, blif_file, edif_file, json_file;
+ bool flatten, vpr, noiopad;
+
+ void clear_flags() override
+ {
+ top_opt = "-auto-top";
+ blif_file = "";
+ edif_file = "";
+ json_file = "";
+ flatten = true;
+ vpr = false;
+ noiopad = false;
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
+ {
+ string run_from, run_to;
+ clear_flags();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-top" && argidx+1 < args.size()) {
+ top_opt = "-top " + args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-blif" && argidx+1 < args.size()) {
+ blif_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+ edif_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-json" && argidx+1 < args.size()) {
+ json_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-run" && argidx+1 < args.size()) {
+ size_t pos = args[argidx+1].find(':');
+ if (pos == std::string::npos)
+ break;
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos+1);
+ continue;
+ }
+ if (args[argidx] == "-flatten") {
+ flatten = true;
+ continue;
+ }
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
+ continue;
+ }
+ if (args[argidx] == "-noiopad") {
+ noiopad = true;
+ continue;
+ }
+ if (args[argidx] == "-vpr") {
+ vpr = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (!design->full_selection())
+ log_cmd_error("This command only operates on fully selected designs!\n");
+
+ log_header(design, "Executing SYNTH_MACHXO2 pass.\n");
+ log_push();
+
+ run_script(design, run_from, run_to);
+
+ log_pop();
+ }
+
+ void script() override
+ {
+ if (check_label("begin"))
+ {
+ run("read_verilog -lib -icells +/machxo2/cells_sim.v");
+ run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+ }
+
+ if (check_label("flatten", "(unless -noflatten)"))
+ {
+ if (flatten || help_mode) {
+ run("proc");
+ run("flatten");
+ run("tribuf -logic");
+ run("deminout");
+ }
+ }
+
+ if (check_label("coarse"))
+ {
+ run("synth -run coarse");
+ }
+
+ if (check_label("fine"))
+ {
+ run("memory_map");
+ run("opt -full");
+ run("techmap -map +/techmap.v");
+ run("opt -fast");
+ }
+
+ if (check_label("map_ios", "(unless -noiopad)"))
+ {
+ if (!noiopad || help_mode)
+ {
+ run("iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD ~T:I:O -tinoutpad $__FACADE_TINOUTPAD ~T:O:I:B A:top");
+ run("attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B]");
+ run("attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]");
+ }
+ }
+
+ if (check_label("map_ffs"))
+ {
+ run("dfflegalize -cell $_DFF_P_ 0");
+ }
+
+ if (check_label("map_luts"))
+ {
+ run("abc -lut 4 -dress");
+ run("clean");
+ }
+
+ if (check_label("map_cells"))
+ {
+ run("techmap -map +/machxo2/cells_map.v");
+ run("clean");
+ }
+
+ if (check_label("check"))
+ {
+ run("hierarchy -check");
+ run("stat");
+ run("blackbox =A:whitebox");
+ }
+
+ if (check_label("blif"))
+ {
+ if (!blif_file.empty() || help_mode) {
+ if (vpr || help_mode) {
+ run(stringf("opt_clean -purge"),
+ " (vpr mode)");
+ run(stringf("write_blif -attr -cname -conn -param %s",
+ help_mode ? "<file-name>" : blif_file.c_str()),
+ " (vpr mode)");
+ }
+ if (!vpr)
+ run(stringf("write_blif -gates -attr -param %s",
+ help_mode ? "<file-name>" : blif_file.c_str()),
+ " (non-vpr mode)");
+ }
+ }
+
+ if (check_label("edif"))
+ {
+ if (!edif_file.empty() || help_mode)
+ run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+ }
+
+ if (check_label("json"))
+ {
+ if (!json_file.empty() || help_mode)
+ run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+ }
+ }
+} SynthMachXO2Pass;
+
+PRIVATE_NAMESPACE_END
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 15:48:12 +0000