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-rw-r--r--techlibs/xilinx/abc_xc7.box22
1 files changed, 17 insertions, 5 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 8c046cdbc..c95ba4969 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -3,17 +3,22 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# F7BMUX slower than F7AMUX
+# Average across F7[AB]MUX
# Inputs: I0 I1 S0
# Outputs: O
-F7BMUX 1 1 3 1
-217 223 296
+F7MUX 1 1 3 1
+204 208 286
# Inputs: I0 I1 S0
# Outputs: O
MUXF8 2 1 3 1
104 94 273
+# Inputs: I0 I1 I2 I3 S0 S1
+# Outputs: O
+MUXF78 10 1 6 1
+190 193 217 223 296 273
+
# CARRY4 + CARRY4_[ABCD]X
# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
@@ -31,15 +36,22 @@ CARRY4 3 1 10 8
580 526 507 398 385 508 528 378 380 114
# SLICEM/A6LUT
+# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
+# Outputs: DPO SPO
+RAM32X1D 4 0 13 2
+- - - - - - 124 124 124 124 124 - -
+124 124 124 124 124 - - - - - - - -
+
+# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
-RAM64X1D 4 0 15 2
+RAM64X1D 5 0 15 2
- - - - - - - 642 631 472 407 238 127 - -
642 631 472 407 238 127 - - - - - - - - -
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
-RAM128X1D 5 0 17 2
+RAM128X1D 6 0 17 2
- - - - - - - - 1009 998 839 774 605 494 450 - -
1047 1036 877 812 643 532 478 - - - - - - - - - -