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-rw-r--r--techlibs/xilinx/cells_sim.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3ed0759db..56eb782c6 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -1185,10 +1185,10 @@ module RAM64M (
output DOB,
output DOC,
output DOD,
- input [4:0] ADDRA,
- input [4:0] ADDRB,
- input [4:0] ADDRC,
- input [4:0] ADDRD,
+ input [5:0] ADDRA,
+ input [5:0] ADDRB,
+ input [5:0] ADDRC,
+ input [5:0] ADDRD,
input DIA,
input DIB,
input DIC,