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-rw-r--r--techlibs/xilinx/cells_sim.v94
1 files changed, 72 insertions, 22 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index bec9ea1a0..973e17212 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -29,24 +29,35 @@ module GND(output G);
assign G = 0;
endmodule
-module IBUF(output O, input I);
+module IBUF(
+ output O,
+ (* iopad_external_pin *)
+ input I);
parameter IOSTANDARD = "default";
parameter IBUF_LOW_PWR = 0;
assign O = I;
endmodule
-module OBUF(output O, input I);
+module OBUF(
+ (* iopad_external_pin *)
+ output O,
+ input I);
parameter IOSTANDARD = "default";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
assign O = I;
endmodule
-module BUFG(output O, input I);
+module BUFG(
+ (* clkbuf_driver *)
+ output O,
+ input I);
+
assign O = I;
endmodule
module BUFGCTRL(
+ (* clkbuf_driver *)
output O,
input I0, input I1,
input S0, input S1,
@@ -72,7 +83,11 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
endmodule
-module BUFHCE(output O, input I, input CE);
+module BUFHCE(
+ (* clkbuf_driver *)
+ output O,
+ input I,
+ input CE);
parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC";
@@ -183,9 +198,11 @@ endmodule
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
- (* abc_carry *) output [3:0] CO,
+ (* abc_carry *)
+ output [3:0] CO,
output [3:0] O,
- (* abc_carry *) input CI,
+ (* abc_carry *)
+ input CI,
input CYINIT,
input [3:0] DI, S
);
@@ -219,7 +236,7 @@ endmodule
`endif
-module FDRE (output reg Q, input C, CE, D, R);
+module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -231,7 +248,7 @@ module FDRE (output reg Q, input C, CE, D, R);
endcase endgenerate
endmodule
-module FDSE (output reg Q, input C, CE, D, S);
+module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -243,7 +260,7 @@ module FDSE (output reg Q, input C, CE, D, S);
endcase endgenerate
endmodule
-module FDCE (output reg Q, input C, CE, D, CLR);
+module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -257,7 +274,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
endcase endgenerate
endmodule
-module FDPE (output reg Q, input C, CE, D, PRE);
+module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -271,25 +288,25 @@ module FDPE (output reg Q, input C, CE, D, PRE);
endcase endgenerate
endmodule
-module FDRE_1 (output reg Q, input C, CE, D, R);
+module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule
-module FDSE_1 (output reg Q, input C, CE, D, S);
+module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
+module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
+module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
@@ -298,9 +315,12 @@ endmodule
(* abc_box_id = 5 *)
module RAM32X1D (
output DPO, SPO,
- (* abc_scc_break *) input D,
+ (* abc_scc_break *)
+ input D,
+ (* clkbuf_sink *)
input WCLK,
- (* abc_scc_break *) input WE,
+ (* abc_scc_break *)
+ input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
@@ -318,9 +338,12 @@ endmodule
(* abc_box_id = 6 *)
module RAM64X1D (
output DPO, SPO,
- (* abc_scc_break *) input D,
+ (* abc_scc_break *)
+ input D,
+ (* clkbuf_sink *)
input WCLK,
- (* abc_scc_break *) input WE,
+ (* abc_scc_break *)
+ input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
@@ -338,9 +361,12 @@ endmodule
(* abc_box_id = 7 *)
module RAM128X1D (
output DPO, SPO,
- (* abc_scc_break *) input D,
+ (* abc_scc_break *)
+ input D,
+ (* clkbuf_sink *)
input WCLK,
- (* abc_scc_break *) input WE,
+ (* abc_scc_break *)
+ input WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;
@@ -354,19 +380,41 @@ endmodule
module SRL16E (
output Q,
+ (* clkbuf_sink *)
+ input CLK,
+ input A0, A1, A2, A3, CE, D
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+ reg [15:0] r = INIT;
+ assign Q = r[{A3,A2,A1,A0}];
+ generate
+ if (IS_CLK_INVERTED) begin
+ always @(negedge CLK) if (CE) r <= { r[14:0], D };
+ end
+ else
+ always @(posedge CLK) if (CE) r <= { r[14:0], D };
+ endgenerate
+endmodule
+
+module SRLC16E (
+ output Q,
+ output Q15,
input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
reg [15:0] r = INIT;
+ assign Q15 = r[15];
assign Q = r[{A3,A2,A1,A0}];
generate
if (IS_CLK_INVERTED) begin
always @(negedge CLK) if (CE) r <= { r[14:0], D };
end
else
- always @(posedge CLK) if (CE) r <= { r[14:0], D };
+ always @(posedge CLK) if (CE) r <= { r[14:0], D };
endgenerate
endmodule
@@ -374,7 +422,9 @@ module SRLC32E (
output Q,
output Q31,
input [4:0] A,
- input CE, CLK, D
+ (* clkbuf_sink *)
+ input CLK,
+ input CE, D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 01:01:34 +0000