1 files changed, 47 insertions, 12 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index ef963793c..7941a94cd 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -320,6 +320,41 @@ module FDRE_1 (
   always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
+module FDRSE (
+  output reg Q,
+  (* clkbuf_sink *)
+  (* invertible_pin = "IS_C_INVERTED" *)
+  input C,
+  (* invertible_pin = "IS_CE_INVERTED" *)
+  input CE,
+  (* invertible_pin = "IS_D_INVERTED" *)
+  input D,
+  (* invertible_pin = "IS_R_INVERTED" *)
+  input R,
+  (* invertible_pin = "IS_S_INVERTED" *)
+  input S
+);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_CE_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter [0:0] IS_S_INVERTED = 1'b0;
+  initial Q <= INIT;
+  wire c = C ^ IS_C_INVERTED;
+  wire ce = CE ^ IS_CE_INVERTED;
+  wire d = D ^ IS_D_INVERTED;
+  wire r = R ^ IS_R_INVERTED;
+  wire s = S ^ IS_S_INVERTED;
+  always @(posedge c)
+    if (r)
+      Q <= 0;
+    else if (s)
+      Q <= 1;
+    else if (ce)
+      Q <= d;
+endmodule
+
 (* abc9_box_id=1003, lib_whitebox, abc9_flop *)
 module FDCE (
   (* abc9_arrival=303 *)
@@ -1193,10 +1228,10 @@ module RAM64M (
   output DOB,
   output DOC,
   output DOD,
-  input [4:0] ADDRA,
-  input [4:0] ADDRB,
-  input [4:0] ADDRC,
-  input [4:0] ADDRD,
+  input [5:0] ADDRA,
+  input [5:0] ADDRB,
+  input [5:0] ADDRC,
+  input [5:0] ADDRD,
   input DIA,
   input DIB,
   input DIC,
@@ -1238,14 +1273,14 @@ module RAM64M8 (
   output DOF,
   output DOG,
   output DOH,
-  input [4:0] ADDRA,
-  input [4:0] ADDRB,
-  input [4:0] ADDRC,
-  input [4:0] ADDRD,
-  input [4:0] ADDRE,
-  input [4:0] ADDRF,
-  input [4:0] ADDRG,
-  input [4:0] ADDRH,
+  input [5:0] ADDRA,
+  input [5:0] ADDRB,
+  input [5:0] ADDRC,
+  input [5:0] ADDRD,
+  input [5:0] ADDRE,
+  input [5:0] ADDRF,
+  input [5:0] ADDRG,
+  input [5:0] ADDRH,
   input DIA,
   input DIB,
   input DIC,