diff options
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 108 |
1 files changed, 66 insertions, 42 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index f5850d8a2..4162160bb 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -455,29 +455,6 @@ module CARRY8( assign CO[7] = S[7] ? CO[6] : DI[7]; endmodule -`ifdef _EXPLICIT_CARRY - -module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S); - parameter CYINIT_FABRIC = 0; - wire CI_COMBINE; - if(CYINIT_FABRIC) begin - assign CI_COMBINE = CI_INIT; - end else begin - assign CI_COMBINE = CI; - end - assign CO_CHAIN = S ? CI_COMBINE : DI; - assign CO_FABRIC = S ? CI_COMBINE : DI; - assign O = S ^ CI_COMBINE; -endmodule - -module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S); - assign CO_CHAIN = S ? CI : DI; - assign CO_FABRIC = S ? CI : DI; - assign O = S ^ CI; -endmodule - -`endif - module ORCY (output O, input CI, I); assign O = CI | I; endmodule @@ -2358,6 +2335,8 @@ parameter integer PREG = 1; // The multiplier. wire signed [35:0] P_MULT; +wire signed [17:0] A_MULT; +wire signed [17:0] B_MULT; assign P_MULT = A_MULT * B_MULT; // The cascade output. @@ -2396,8 +2375,6 @@ always @(posedge CLK) begin end // The register enables. -wire signed [17:0] A_MULT; -wire signed [17:0] B_MULT; assign A_MULT = (AREG == 1) ? A_REG : A; assign B_MULT = (BREG == 1) ? B_REG : B_MUX; assign P = (PREG == 1) ? P_REG : P_MULT; @@ -3037,8 +3014,12 @@ endmodule // Virtex 6, Series 7. `ifdef YOSYS -(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG), - lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) *) +(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) +`ifdef ALLOW_WHITEBOX_DSP48E1 + // Do not make DSP48E1 a whitebox for ABC9 even if fully combinatorial, since it is a big complex block + , lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG || INMODEREG || OPMODEREG || ALUMODEREG || CARRYINREG || CARRYINSELREG) +`endif +*) `endif module DSP48E1 ( output [29:0] ACOUT, @@ -3526,11 +3507,15 @@ module DSP48E1 ( if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); `endif end - 2'b10: begin X = P; + 2'b10: + if (PREG == 1) + X = P; + else begin + X = 48'bx; `ifndef YOSYS - if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10"); + $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10"); `endif - end + end 2'b11: X = $signed({Ar2, Br2}); default: X = 48'bx; endcase @@ -3552,20 +3537,36 @@ module DSP48E1 ( case (OPMODEr[6:4]) 3'b000: Z = 48'b0; 3'b001: Z = PCIN; - 3'b010: begin Z = P; + 3'b010: + if (PREG == 1) + Z = P; + else begin + Z = 48'bx; `ifndef YOSYS - if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010"); + $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b010"); `endif - end + end 3'b011: Z = Cr; - 3'b100: begin Z = P; + 3'b100: + if (PREG == 1 && OPMODEr[3:0] === 4'b1000) + Z = P; + else begin + Z = 48'bx; `ifndef YOSYS - if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); - if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100"); + if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); + if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100"); `endif - end + end 3'b101: Z = $signed(PCIN[47:17]); - 3'b110: Z = $signed(P[47:17]); + 3'b110: + if (PREG == 1) + Z = $signed(P[47:17]); + else begin + Z = 48'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b110"); +`endif + end default: Z = 48'bx; endcase end @@ -3591,10 +3592,34 @@ module DSP48E1 ( 3'b001: cin_muxed = ~PCIN[47]; 3'b010: cin_muxed = CARRYCASCIN; 3'b011: cin_muxed = PCIN[47]; - 3'b100: cin_muxed = CARRYCASCOUT; - 3'b101: cin_muxed = ~P[47]; + 3'b100: + if (PREG == 1) + cin_muxed = CARRYCASCOUT; + else begin + cin_muxed = 1'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b100"); +`endif + end + 3'b101: + if (PREG == 1) + cin_muxed = ~P[47]; + else begin + cin_muxed = 1'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b101"); +`endif + end 3'b110: cin_muxed = A24_xnor_B17; - 3'b111: cin_muxed = P[47]; + 3'b111: + if (PREG == 1) + cin_muxed = P[47]; + else begin + cin_muxed = 1'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b111"); +`endif + end default: cin_muxed = 1'bx; endcase end @@ -4186,4 +4211,3 @@ module RAMB36E1 ( if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 882; endspecify endmodule - |