aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx/cells_sim.v
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
-rw-r--r--techlibs/xilinx/cells_sim.v193
1 files changed, 139 insertions, 54 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index c27b0f02b..22dca3c47 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -325,6 +325,7 @@ endmodule
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
+(* abc9_box_id=1100, lib_whitebox, abc9_flop *)
module FDRE (
(* abc9_arrival=303 *)
output reg Q,
@@ -348,6 +349,20 @@ module FDRE (
endcase endgenerate
endmodule
+(* abc9_box_id=1101, lib_whitebox, abc9_flop *)
+module FDRE_1 (
+ (* abc9_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, R
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q <= INIT;
+ always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
+endmodule
+
+(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
module FDSE (
(* abc9_arrival=303 *)
output reg Q,
@@ -371,6 +386,19 @@ module FDSE (
endcase endgenerate
endmodule
+(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
+module FDSE_1 (
+ (* abc9_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, S
+);
+ parameter [0:0] INIT = 1'b1;
+ initial Q <= INIT;
+ always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
+endmodule
+
module FDRSE (
output reg Q,
(* clkbuf_sink *)
@@ -406,6 +434,7 @@ module FDRSE (
Q <= d;
endmodule
+(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
module FDCE (
(* abc9_arrival=303 *)
output reg Q,
@@ -413,10 +442,10 @@ module FDCE (
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
- (* invertible_pin = "IS_D_INVERTED" *)
- input D,
(* invertible_pin = "IS_CLR_INVERTED" *)
- input CLR
+ input CLR,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -431,6 +460,20 @@ module FDCE (
endcase endgenerate
endmodule
+(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
+module FDCE_1 (
+ (* abc9_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, CLR
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q <= INIT;
+ always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+endmodule
+
+(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
module FDPE (
(* abc9_arrival=303 *)
output reg Q,
@@ -456,6 +499,19 @@ module FDPE (
endcase endgenerate
endmodule
+(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
+module FDPE_1 (
+ (* abc9_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, PRE
+);
+ parameter [0:0] INIT = 1'b1;
+ initial Q <= INIT;
+ always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+endmodule
+
module FDCPE (
output wire Q,
(* clkbuf_sink *)
@@ -501,54 +557,6 @@ module FDCPE (
assign Q = qs ? qp : qc;
endmodule
-module FDRE_1 (
- (* abc9_arrival=303 *)
- output reg Q,
- (* clkbuf_sink *)
- input C,
- input CE, D, R
-);
- parameter [0:0] INIT = 1'b0;
- initial Q <= INIT;
- always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
-endmodule
-
-module FDSE_1 (
- (* abc9_arrival=303 *)
- output reg Q,
- (* clkbuf_sink *)
- input C,
- input CE, D, S
-);
- parameter [0:0] INIT = 1'b1;
- initial Q <= INIT;
- always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
-endmodule
-
-module FDCE_1 (
- (* abc9_arrival=303 *)
- output reg Q,
- (* clkbuf_sink *)
- input C,
- input CE, D, CLR
-);
- parameter [0:0] INIT = 1'b0;
- initial Q <= INIT;
- always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
-endmodule
-
-module FDPE_1 (
- (* abc9_arrival=303 *)
- output reg Q,
- (* clkbuf_sink *)
- input C,
- input CE, D, PRE
-);
- parameter [0:0] INIT = 1'b1;
- initial Q <= INIT;
- always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
-endmodule
-
module LDCE (
output reg Q,
(* invertible_pin = "IS_CLR_INVERTED" *)
@@ -2160,9 +2168,15 @@ module DSP48E1 (
output reg [3:0] CARRYOUT,
output reg MULTSIGNOUT,
output OVERFLOW,
+`ifdef YOSYS
+ (* abc9_arrival = \DSP48E1.P_arrival () *)
+`endif
output reg signed [47:0] P,
output reg PATTERNBDETECT,
output reg PATTERNDETECT,
+`ifdef YOSYS
+ (* abc9_arrival = \DSP48E1.PCOUT_arrival () *)
+`endif
output [47:0] PCOUT,
output UNDERFLOW,
input signed [29:0] A,
@@ -2235,6 +2249,77 @@ module DSP48E1 (
parameter [4:0] IS_INMODE_INVERTED = 5'b0;
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
+`ifdef YOSYS
+ function integer \DSP48E1.P_arrival ;
+ begin
+ \DSP48E1.P_arrival = 0;
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
+ if (PREG != 0) \DSP48E1.P_arrival = 329;
+ // Worst-case from CREG and MREG
+ else if (CREG != 0) \DSP48E1.P_arrival = 1687;
+ else if (MREG != 0) \DSP48E1.P_arrival = 1671;
+ // Worst-case from AREG and BREG
+ else if (AREG != 0) \DSP48E1.P_arrival = 2952;
+ else if (BREG != 0) \DSP48E1.P_arrival = 2813;
+ end
+ else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
+ if (PREG != 0) \DSP48E1.P_arrival = 329;
+ // Worst-case from CREG and MREG
+ else if (CREG != 0) \DSP48E1.P_arrival = 1687;
+ else if (MREG != 0) \DSP48E1.P_arrival = 1671;
+ // Worst-case from AREG, ADREG, BREG, DREG
+ else if (AREG != 0) \DSP48E1.P_arrival = 3935;
+ else if (DREG != 0) \DSP48E1.P_arrival = 3908;
+ else if (ADREG != 0) \DSP48E1.P_arrival = 2958;
+ else if (BREG != 0) \DSP48E1.P_arrival = 2813;
+ end
+ else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
+ if (PREG != 0) \DSP48E1.P_arrival = 329;
+ // Worst-case from AREG, BREG, CREG
+ else if (CREG != 0) \DSP48E1.P_arrival = 1687;
+ else if (AREG != 0) \DSP48E1.P_arrival = 1632;
+ else if (BREG != 0) \DSP48E1.P_arrival = 1616;
+ end
+ //else
+ // $error("Invalid DSP48E1 configuration");
+ end
+ endfunction
+ function integer \DSP48E1.PCOUT_arrival ;
+ begin
+ \DSP48E1.PCOUT_arrival = 0;
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
+ if (PREG != 0) \DSP48E1.PCOUT_arrival = 435;
+ // Worst-case from CREG and MREG
+ else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
+ else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819;
+ // Worst-case from AREG and BREG
+ else if (AREG != 0) \DSP48E1.PCOUT_arrival = 3098;
+ else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960;
+ end
+ else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
+ if (PREG != 0) \DSP48E1.PCOUT_arrival = 435;
+ // Worst-case from CREG and MREG
+ else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
+ else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819;
+ // Worst-case from AREG, ADREG, BREG, DREG
+ else if (AREG != 0) \DSP48E1.PCOUT_arrival = 4083;
+ else if (DREG != 0) \DSP48E1.PCOUT_arrival = 4056;
+ else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960;
+ else if (ADREG != 0) \DSP48E1.PCOUT_arrival = 2859;
+ end
+ else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
+ if (PREG != 0) \DSP48E1.PCOUT_arrival = 435;
+ // Worst-case from AREG, BREG, CREG
+ else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
+ else if (AREG != 0) \DSP48E1.PCOUT_arrival = 1780;
+ else if (BREG != 0) \DSP48E1.PCOUT_arrival = 1765;
+ end
+ //else
+ // $error("Invalid DSP48E1 configuration");
+ end
+ endfunction
+`endif
+
initial begin
`ifndef YOSYS
if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
@@ -2311,8 +2396,8 @@ module DSP48E1 (
if (CEB2) Br2 <= Br1;
end
end else if (BREG == 1) begin
- //initial Br1 = 25'b0;
- initial Br2 = 25'b0;
+ //initial Br1 = 18'b0;
+ initial Br2 = 18'b0;
always @(posedge CLK)
if (RSTB) begin
Br1 <= 18'b0;
@@ -2359,7 +2444,7 @@ module DSP48E1 (
endgenerate
// A/D input selection and pre-adder
- wire signed [29:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2;
+ wire signed [24:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2;
wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed;
wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0;
wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated);
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 03:45:56 +0000