1 files changed, 15 insertions, 15 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index e4c580b9d..06e982a0e 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -65,9 +65,9 @@ CELLS = [
 
     # CLB -- registers/latches.
     # Virtex 1/2/4/5, Spartan 3.
-    Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}),
-    Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}),
-    Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}),
+    # Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}),
+    # Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}),
+    # Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}),
     # Virtex 6, Spartan 6, Series 7, Ultrascale.
     # Cell('FDCE'),
     # Cell('FDPE'),
@@ -75,8 +75,8 @@ CELLS = [
     # Cell('FDSE'),
     # Cell('LDCE'),
     # Cell('LDPE'),
-    Cell('AND2B1L'),
-    Cell('OR2L'),
+    # Cell('AND2B1L'),
+    # Cell('OR2L'),
 
     # CLB -- other.
     # Cell('LUT1'),
@@ -86,23 +86,23 @@ CELLS = [
     # Cell('LUT5'),
     # Cell('LUT6'),
     # Cell('LUT6_2'),
-    Cell('MUXF5'),
-    Cell('MUXF6'),
+    # Cell('MUXF5'),
+    # Cell('MUXF6'),
     # Cell('MUXF7'),
     # Cell('MUXF8'),
-    Cell('MUXF9'),
+    # Cell('MUXF9'),
     # Cell('CARRY4'),
-    Cell('CARRY8'),
+    # Cell('CARRY8'),
     # Cell('MUXCY'),
     # Cell('XORCY'),
-    Cell('ORCY'),
-    Cell('MULT_AND'),
-    Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('ORCY'),
+    # Cell('MULT_AND'),
+    # Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}),
     # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
-    Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}),
     # Cell('SRLC16E', port_attrs={'CLK': ['clkbuf_sink']}),
     # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
-    Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+    # Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
 
     # Block RAM.
     # Virtex.
@@ -209,7 +209,7 @@ CELLS = [
     # Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E
     # Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP
     # Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6
-    Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4
+    # Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4
     Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5
     #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7
     Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}), # Ultrascale