diff options
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 69 |
1 files changed, 35 insertions, 34 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 82e403f78..e4c580b9d 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -28,40 +28,40 @@ CELLS = [ # - UG974 (Ultrascale) # CLB -- RAM/ROM. - Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('ROM16X1'), - Cell('ROM32X1'), - Cell('ROM64X1'), - Cell('ROM128X1'), - Cell('ROM256X1'), + # Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('ROM16X1'), + # Cell('ROM32X1'), + # Cell('ROM64X1'), + # Cell('ROM128X1'), + # Cell('ROM256X1'), # CLB -- registers/latches. # Virtex 1/2/4/5, Spartan 3. @@ -372,6 +372,7 @@ CELLS = [ Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}), Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}), # Clock buffers (IO and regional) -- Virtex. |