diff options
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 38 |
1 files changed, 5 insertions, 33 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 06e982a0e..749b1e0a7 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -144,23 +144,9 @@ CELLS = [ Cell('RAMB16BWE_S36_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), Cell('RAMB16BWE_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), # Spartan 3A DSP. - Cell('RAMB16BWER', port_attrs={ - 'CLKA': ['clkbuf_sink'], - 'CLKB': ['clkbuf_sink'], - #'DOA': ['abc9_arrival=<TODO>'], - #'DOB': ['abc9_arrival=<TODO>'], - #'DOPA': ['abc9_arrival=<TODO>'], - #'DOPB': ['abc9_arrival=<TODO>'], - }), + Cell('RAMB16BWER', port_attrs={ 'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), # Spartan 6 (in addition to above). - Cell('RAMB8BWER', port_attrs={ - 'CLKAWRCLK': ['clkbuf_sink'], - 'CLKBRDCLK': ['clkbuf_sink'], - #'DOADO': ['abc9_arrival=<TODO>'], - #'DOBDO': ['abc9_arrival=<TODO>'], - #'DOPADOP': ['abc9_arrival=<TODO>'], - #'DOPBDOP': ['abc9_arrival=<TODO>'], - }), + Cell('RAMB8BWER', port_attrs={ 'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}), # Virtex 4. Cell('FIFO16', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), Cell('RAMB16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), @@ -177,22 +163,8 @@ CELLS = [ # Virtex 6 / Series 7. Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('RAMB18E1', port_attrs={ - 'CLKARDCLK': ['clkbuf_sink'], - 'CLKBWRCLK': ['clkbuf_sink'], - 'DOADO': ['abc9_arrival=2454'], - 'DOBDO': ['abc9_arrival=2454'], - 'DOPADOP': ['abc9_arrival=2454'], - 'DOPBDOP': ['abc9_arrival=2454'], - }), - Cell('RAMB36E1', port_attrs={ - 'CLKARDCLK': ['clkbuf_sink'], - 'CLKBWRCLK': ['clkbuf_sink'], - 'DOADO': ['abc9_arrival=2454'], - 'DOBDO': ['abc9_arrival=2454'], - 'DOPADOP': ['abc9_arrival=2454'], - 'DOPBDOP': ['abc9_arrival=2454'], - }), + #Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), + #Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}), # Ultrascale. Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), @@ -336,7 +308,7 @@ CELLS = [ Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), # Output. # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}), Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), |