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-rw-r--r--techlibs/xilinx/cells_xtra.v750
1 files changed, 0 insertions, 750 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 00a8a5f8a..c3e5c72f9 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -1,755 +1,5 @@
// Created by cells_xtra.py from Xilinx models
-module RAM16X1S (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X1S_1 (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1S (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1S_1 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1S (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1S_1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM128X1S (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM128X1S_1 (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM256X1S (...);
- parameter [255:0] INIT = 256'h0;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input [7:0] A;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM512X1S (...);
- parameter [511:0] INIT = 512'h0;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input [8:0] A;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X2S (...);
- parameter [15:0] INIT_00 = 16'h0000;
- parameter [15:0] INIT_01 = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- input A0;
- input A1;
- input A2;
- input A3;
- input D0;
- input D1;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X2S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D0;
- input D1;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X2S (...);
- parameter [63:0] INIT_00 = 64'h0000000000000000;
- parameter [63:0] INIT_01 = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D0;
- input D1;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X4S (...);
- parameter [15:0] INIT_00 = 16'h0000;
- parameter [15:0] INIT_01 = 16'h0000;
- parameter [15:0] INIT_02 = 16'h0000;
- parameter [15:0] INIT_03 = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- output O2;
- output O3;
- input A0;
- input A1;
- input A2;
- input A3;
- input D0;
- input D1;
- input D2;
- input D3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X4S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [31:0] INIT_02 = 32'h00000000;
- parameter [31:0] INIT_03 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- output O2;
- output O3;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D0;
- input D1;
- input D2;
- input D3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X8S (...);
- parameter [15:0] INIT_00 = 16'h0000;
- parameter [15:0] INIT_01 = 16'h0000;
- parameter [15:0] INIT_02 = 16'h0000;
- parameter [15:0] INIT_03 = 16'h0000;
- parameter [15:0] INIT_04 = 16'h0000;
- parameter [15:0] INIT_05 = 16'h0000;
- parameter [15:0] INIT_06 = 16'h0000;
- parameter [15:0] INIT_07 = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [7:0] O;
- input A0;
- input A1;
- input A2;
- input A3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
- input [7:0] D;
-endmodule
-
-module RAM32X8S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [31:0] INIT_02 = 32'h00000000;
- parameter [31:0] INIT_03 = 32'h00000000;
- parameter [31:0] INIT_04 = 32'h00000000;
- parameter [31:0] INIT_05 = 32'h00000000;
- parameter [31:0] INIT_06 = 32'h00000000;
- parameter [31:0] INIT_07 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [7:0] O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
- input [7:0] D;
-endmodule
-
-module RAM16X1D (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X1D_1 (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1D_1 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- input DPRA4;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1D_1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- input DPRA4;
- input DPRA5;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM256X1D (...);
- parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input [7:0] A;
- input D;
- input [7:0] DPRA;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32M (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [1:0] DOA;
- output [1:0] DOB;
- output [1:0] DOC;
- output [1:0] DOD;
- input [4:0] ADDRA;
- input [4:0] ADDRB;
- input [4:0] ADDRC;
- input [4:0] ADDRD;
- input [1:0] DIA;
- input [1:0] DIB;
- input [1:0] DIC;
- input [1:0] DID;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32M16 (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [63:0] INIT_E = 64'h0000000000000000;
- parameter [63:0] INIT_F = 64'h0000000000000000;
- parameter [63:0] INIT_G = 64'h0000000000000000;
- parameter [63:0] INIT_H = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [1:0] DOA;
- output [1:0] DOB;
- output [1:0] DOC;
- output [1:0] DOD;
- output [1:0] DOE;
- output [1:0] DOF;
- output [1:0] DOG;
- output [1:0] DOH;
- input [4:0] ADDRA;
- input [4:0] ADDRB;
- input [4:0] ADDRC;
- input [4:0] ADDRD;
- input [4:0] ADDRE;
- input [4:0] ADDRF;
- input [4:0] ADDRG;
- input [4:0] ADDRH;
- input [1:0] DIA;
- input [1:0] DIB;
- input [1:0] DIC;
- input [1:0] DID;
- input [1:0] DIE;
- input [1:0] DIF;
- input [1:0] DIG;
- input [1:0] DIH;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64M (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DOA;
- output DOB;
- output DOC;
- output DOD;
- input [5:0] ADDRA;
- input [5:0] ADDRB;
- input [5:0] ADDRC;
- input [5:0] ADDRD;
- input DIA;
- input DIB;
- input DIC;
- input DID;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64M8 (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [63:0] INIT_E = 64'h0000000000000000;
- parameter [63:0] INIT_F = 64'h0000000000000000;
- parameter [63:0] INIT_G = 64'h0000000000000000;
- parameter [63:0] INIT_H = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DOA;
- output DOB;
- output DOC;
- output DOD;
- output DOE;
- output DOF;
- output DOG;
- output DOH;
- input [5:0] ADDRA;
- input [5:0] ADDRB;
- input [5:0] ADDRC;
- input [5:0] ADDRD;
- input [5:0] ADDRE;
- input [5:0] ADDRF;
- input [5:0] ADDRG;
- input [5:0] ADDRH;
- input DIA;
- input DIB;
- input DIC;
- input DID;
- input DIE;
- input DIF;
- input DIG;
- input DIH;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module ROM16X1 (...);
- parameter [127:0] INIT = 16'h0000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
-endmodule
-
-module ROM32X1 (...);
- parameter [31:0] INIT = 32'h00000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
-endmodule
-
-module ROM64X1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
-endmodule
-
-module ROM128X1 (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
-endmodule
-
-module ROM256X1 (...);
- parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
- input A7;
-endmodule
-
-module FDCPE (...);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_CLR_INVERTED = 1'b0;
- parameter [0:0] IS_PRE_INVERTED = 1'b0;
- output Q;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_C_INVERTED" *)
- input C;
- input CE;
- (* invertible_pin = "IS_CLR_INVERTED" *)
- input CLR;
- input D;
- (* invertible_pin = "IS_PRE_INVERTED" *)
- input PRE;
-endmodule
-
-module FDRSE (...);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_CE_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_R_INVERTED = 1'b0;
- parameter [0:0] IS_S_INVERTED = 1'b0;
- output Q;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_C_INVERTED" *)
- input C;
- (* invertible_pin = "IS_CE_INVERTED" *)
- input CE;
- (* invertible_pin = "IS_D_INVERTED" *)
- input D;
- (* invertible_pin = "IS_R_INVERTED" *)
- input R;
- (* invertible_pin = "IS_S_INVERTED" *)
- input S;
-endmodule
-
-module LDCPE (...);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_CLR_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_G_INVERTED = 1'b0;
- parameter [0:0] IS_GE_INVERTED = 1'b0;
- parameter [0:0] IS_PRE_INVERTED = 1'b0;
- output Q;
- (* invertible_pin = "IS_CLR_INVERTED" *)
- input CLR;
- (* invertible_pin = "IS_D_INVERTED" *)
- input D;
- (* invertible_pin = "IS_G_INVERTED" *)
- input G;
- (* invertible_pin = "IS_GE_INVERTED" *)
- input GE;
- (* invertible_pin = "IS_PRE_INVERTED" *)
- input PRE;
-endmodule
-
-module AND2B1L (...);
- parameter [0:0] IS_SRI_INVERTED = 1'b0;
- output O;
- input DI;
- (* invertible_pin = "IS_SRI_INVERTED" *)
- input SRI;
-endmodule
-
-module OR2L (...);
- parameter [0:0] IS_SRI_INVERTED = 1'b0;
- output O;
- input DI;
- (* invertible_pin = "IS_SRI_INVERTED" *)
- input SRI;
-endmodule
-
-module MUXF5 (...);
- output O;
- input I0;
- input I1;
- input S;
-endmodule
-
-module MUXF6 (...);
- output O;
- input I0;
- input I1;
- input S;
-endmodule
-
-module MUXF9 (...);
- output O;
- input I0;
- input I1;
- input S;
-endmodule
-
-module CARRY8 (...);
- parameter CARRY_TYPE = "SINGLE_CY8";
- output [7:0] CO;
- output [7:0] O;
- input CI;
- input CI_TOP;
- input [7:0] DI;
- input [7:0] S;
-endmodule
-
-module ORCY (...);
- output O;
- input CI;
- input I;
-endmodule
-
-module MULT_AND (...);
- output LO;
- input I0;
- input I1;
-endmodule
-
-module SRL16 (...);
- parameter [15:0] INIT = 16'h0000;
- output Q;
- input A0;
- input A1;
- input A2;
- input A3;
- (* clkbuf_sink *)
- input CLK;
- input D;
-endmodule
-
-module SRLC16 (...);
- parameter [15:0] INIT = 16'h0000;
- output Q;
- output Q15;
- input A0;
- input A1;
- input A2;
- input A3;
- (* clkbuf_sink *)
- input CLK;
- input D;
-endmodule
-
-module CFGLUT5 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- output CDO;
- output O5;
- output O6;
- input I4;
- input I3;
- input I2;
- input I1;
- input I0;
- input CDI;
- input CE;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_CLK_INVERTED" *)
- input CLK;
-endmodule
-
module RAMB16_S1 (...);
parameter [0:0] INIT = 1'h0;
parameter [0:0] SRVAL = 1'h0;
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