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Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc106
1 files changed, 76 insertions, 30 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a5358cf64..b5c203d1f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -46,7 +46,7 @@ struct SynthXilinxPass : public ScriptPass
log(" -top <module>\n");
log(" use the specified module as top module\n");
log("\n");
- log(" -family {xcup|xcu|xc7|xc6v|xc6s}\n");
+ log(" -family {xcup|xcu|xc7|xc6v|xc5v|xc6s}\n");
log(" run synthesis for the specified Xilinx architecture\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" default: xc7\n");
@@ -93,6 +93,9 @@ struct SynthXilinxPass : public ScriptPass
log(" -noclkbuf\n");
log(" disable automatic clock buffer insertion\n");
log("\n");
+ log(" -uram\n");
+ log(" infer URAM288s for large memories (xcup only)\n");
+ log("\n");
log(" -widemux <int>\n");
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
@@ -119,7 +122,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
- bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, abc9;
+ bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9;
bool flatten_before_abc;
int widemux;
@@ -143,6 +146,7 @@ struct SynthXilinxPass : public ScriptPass
nocarry = false;
nowidelut = false;
nodsp = false;
+ uram = false;
abc9 = false;
flatten_before_abc = false;
widemux = 0;
@@ -248,11 +252,15 @@ struct SynthXilinxPass : public ScriptPass
nodsp = true;
continue;
}
+ if (args[argidx] == "-uram") {
+ uram = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
- if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s")
+ if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc5v" && family != "xc6s")
log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
if (widemux != 0 && widemux < 2)
@@ -289,24 +297,7 @@ struct SynthXilinxPass : public ScriptPass
read_args += " -lib +/xilinx/cells_sim.v";
run("read_verilog" + read_args);
- if (help_mode)
- run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
- else if (family == "xc6s")
- run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v");
- else if (family == "xc6v")
- run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v");
- else if (family == "xc7")
- run("read_verilog -lib +/xilinx/xc7_cells_xtra.v");
- else if (family == "xcu" || family == "xcup")
- run("read_verilog -lib +/xilinx/xcu_cells_xtra.v");
-
- if (help_mode) {
- run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
- } else if (family == "xc6s") {
- run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
- } else if (family == "xc6v" || family == "xc7") {
- run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
- }
+ run("read_verilog -lib +/xilinx/cells_xtra.v");
run(stringf("hierarchy -check %s", top_opt.c_str()));
}
@@ -342,15 +333,53 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_dsp", "(skip if '-nodsp')")) {
if (!nodsp || help_mode) {
+ run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first
// NB: Xilinx multipliers are signed only
- run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 "
- "-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally
- // limited to 18x18 in order to take
- // advantage of the (PCOUT << 17) -> PCIN
- // dedicated cascade chain capability
- "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
- "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
- "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+ if (help_mode)
+ run("techmap -map +/mul2dsp.v -map +/xilinx/{family}_dsp_map.v {options}");
+ else if (family == "xc2v" || family == "xc3s" || family == "xc3se" || family == "xc3sa")
+ run("techmap -map +/mul2dsp.v -map +/xilinx/xc3s_mult_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
+ "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+ "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+ "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
+ else if (family == "xc3sda")
+ run("techmap -map +/mul2dsp.v -map +/xilinx/xc3sda_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
+ "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+ "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+ "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
+ else if (family == "xc6s")
+ run("techmap -map +/mul2dsp.v -map +/xilinx/xc6s_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
+ "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+ "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+ "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
+ else if (family == "xc4v")
+ run("techmap -map +/mul2dsp.v -map +/xilinx/xc4v_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
+ "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+ "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+ "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
+ else if (family == "xc5v")
+ run("techmap -map +/mul2dsp.v -map +/xilinx/xc5v_dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 "
+ "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+ "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+ "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+ else if (family == "xc6v" || family == "xc7")
+ run("techmap -map +/mul2dsp.v -map +/xilinx/xc7_dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 "
+ "-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
+ // limited to 18x18 in order to take
+ // advantage of the (PCOUT << 17) -> PCIN
+ // dedicated cascade chain capability
+ "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+ "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+ "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
+ else if (family == "xcu" || family == "xcup")
+ run("techmap -map +/mul2dsp.v -map +/xilinx/xcu_dsp_map.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=18 "
+ "-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
+ // limited to 18x18 in order to take
+ // advantage of the (PCOUT << 17) -> PCIN
+ // dedicated cascade chain capability
+ "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
+ "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
+ "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL27X18");
run("select a:mul2dsp");
run("setattr -unset mul2dsp");
run("opt_expr -fine");
@@ -371,6 +400,20 @@ struct SynthXilinxPass : public ScriptPass
run("opt_clean");
}
+ if (check_label("map_uram", "(only if '-uram')")) {
+ if (help_mode) {
+ run("memory_bram -rules +/xilinx/{family}_urams.txt");
+ run("techmap -map +/xilinx/{family}_urams_map.v");
+ } else if (uram) {
+ if (family == "xcup") {
+ run("memory_bram -rules +/xilinx/xcup_urams.txt");
+ run("techmap -map +/xilinx/xcup_urams_map.v");
+ } else {
+ log_warning("UltraRAM inference not supported for family %s.\n", family.c_str());
+ }
+ }
+ }
+
if (check_label("map_bram", "(skip if '-nobram')")) {
if (help_mode) {
run("memory_bram -rules +/xilinx/{family}_brams.txt");
@@ -380,8 +423,11 @@ struct SynthXilinxPass : public ScriptPass
run("memory_bram -rules +/xilinx/xc6s_brams.txt");
run("techmap -map +/xilinx/xc6s_brams_map.v");
} else if (family == "xc6v" || family == "xc7") {
- run("memory_bram -rules +/xilinx/xc7_brams.txt");
+ run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
run("techmap -map +/xilinx/xc7_brams_map.v");
+ } else if (family == "xcu" || family == "xcup") {
+ run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
+ run("techmap -map +/xilinx/xcu_brams_map.v");
} else {
log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-01 23:30:53 +0000