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-rw-r--r--techlibs/xilinx/synth_xilinx.cc9
1 files changed, 6 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3d4a65c5d..7105ba429 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -291,10 +291,11 @@ struct SynthXilinxPass : public ScriptPass
ff_map_file = "+/xilinx/xc7_ff_map.v";
if (check_label("begin")) {
+ std::string read_args;
if (vpr)
- run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
- else
- run("read_verilog -lib +/xilinx/cells_sim.v");
+ read_args += " -D_EXPLICIT_CARRY";
+ read_args += " -lib +/xilinx/cells_sim.v";
+ run("read_verilog" + read_args);
run("read_verilog -lib +/xilinx/cells_xtra.v");
@@ -512,6 +513,7 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_ffs")) {
if (abc9 || help_mode) {
+ run("clkpart -set_attr clkpart 1", "('-abc9' only)");
run("techmap -map " + ff_map_file, "('-abc9' only)");
}
}
@@ -536,6 +538,7 @@ struct SynthXilinxPass : public ScriptPass
else
abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
run("abc9" + abc9_opts);
+ run("clkpart -unpart clkpart");
}
else {
if (nowidelut)