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-rw-r--r--techlibs/xilinx/synth_xilinx.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c10e42532..d5e9b80c8 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -282,8 +282,8 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "opt -full");
- Pass::call(design, "techmap -map +/techmap.v");
Pass::call(design, "read_verilog +/xilinx/cells_box.v");
+ Pass::call(design, "techmap -map +/techmap.v");
if (abc == "abc9")
Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
else