diff options
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 50 |
1 files changed, 41 insertions, 9 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 8aa7b508e..bde95c638 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -54,6 +54,9 @@ struct SynthXilinxPass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); + log(" -nocarry\n"); + log(" disable inference of carry chains\n"); + log("\n"); log(" -nobram\n"); log(" disable inference of block rams\n"); log("\n"); @@ -63,6 +66,9 @@ struct SynthXilinxPass : public ScriptPass log(" -nosrl\n"); log(" disable inference of shift registers\n"); log("\n"); + log(" -nomux\n"); + log(" disable inference of wide multiplexers\n"); + log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -74,26 +80,31 @@ struct SynthXilinxPass : public ScriptPass log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); + log(" -abc9\n"); + log(" use abc9 instead of abc\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - std::string top_opt, edif_file, blif_file; - bool flatten, retime, vpr, nobram, nodram, nosrl; + std::string top_opt, edif_file, blif_file, abc; + bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux; void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; edif_file.clear(); blif_file.clear(); + abc = "abc"; flatten = false; retime = false; vpr = false; nobram = false; nodram = false; nosrl = false; + nomux = false; } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -136,6 +147,10 @@ struct SynthXilinxPass : public ScriptPass vpr = true; continue; } + if (args[argidx] == "-nocarry") { + nocarry = true; + continue; + } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -148,6 +163,14 @@ struct SynthXilinxPass : public ScriptPass nosrl = true; continue; } + if (args[argidx] == "-nomux") { + nomux = true; + continue; + } + if (args[argidx] == "-abc9") { + abc = "abc9"; + continue; + } break; } extra_args(args, argidx, design); @@ -206,10 +229,11 @@ struct SynthXilinxPass : public ScriptPass if (check_label("fine")) { // shregmap -tech xilinx can cope with $shiftx and $mux - // cells for identifiying variable-length shift registers, + // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former - if (!nosrl || help_mode) - run("pmux2shiftx", "(skip if '-nosrl')"); + // Also: wide multiplexer inference benefits from this too + if (!nosrl || !nomux) + run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')"); run("opt -fast -full"); run("memory_map"); @@ -232,18 +256,26 @@ struct SynthXilinxPass : public ScriptPass run("techmap"); run("opt -fast"); + + if (!nomux || help_mode) + run("muxcover -mux8 -mux16"); } if (check_label("map_cells")) { - run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); + std::string define; + if (nomux) + define += " -D NO_MUXFN"; + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v" + define); run("clean"); } if (check_label("map_luts")) { - if (help_mode) - run("abc -luts 2:2,3,6:5,10,20 [-dff]"); + if (abc == "abc9") + run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : "")); + else if (help_mode) + run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); else - run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); run("clean"); // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming |