diff options
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7085214de..41429b338 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -339,7 +339,7 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); } - if (check_label("map_dsp"), "(skip if '-nodsp')") { + if (check_label("map_dsp", "(skip if '-nodsp')")) { if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " @@ -477,10 +477,14 @@ struct SynthXilinxPass : public ScriptPass log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n"); run("techmap -map +/xilinx/abc_map.v -max_iter 1"); run("read_verilog -icells -lib +/xilinx/abc_model.v"); + std::string abc9_opts = " -box +/xilinx/abc_xc7.box"; + abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); + abc9_opts += " -nomfs"; if (nowidelut) - run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut"; else - run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc_xc7.lut"; + run("abc9" + abc9_opts); } else { if (nowidelut) |