diff options
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3d4a65c5d..5bc55387b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -291,10 +291,11 @@ struct SynthXilinxPass : public ScriptPass ff_map_file = "+/xilinx/xc7_ff_map.v"; if (check_label("begin")) { + std::string read_args; if (vpr) - run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); - else - run("read_verilog -lib +/xilinx/cells_sim.v"); + read_args += " -D_EXPLICIT_CARRY"; + read_args += " -lib +/xilinx/cells_sim.v"; + run("read_verilog" + read_args); run("read_verilog -lib +/xilinx/cells_xtra.v"); @@ -512,6 +513,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_ffs")) { if (abc9 || help_mode) { + run("clkpart -set_attr clkpart 1", "('-abc9' only)"); run("techmap -map " + ff_map_file, "('-abc9' only)"); } } @@ -536,14 +538,16 @@ struct SynthXilinxPass : public ScriptPass else abc9_opts += " -lut +/xilinx/abc9_xc7.lut"; run("abc9" + abc9_opts); + run("clean"); + run("clkpart -unpart clkpart"); } else { if (nowidelut) run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + run("clean"); } - run("clean"); // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming @@ -557,7 +561,6 @@ struct SynthXilinxPass : public ScriptPass else techmap_args += " -map " + ff_map_file; run("techmap " + techmap_args); - run("clean"); } if (check_label("finalize")) { @@ -572,6 +575,7 @@ struct SynthXilinxPass : public ScriptPass run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')"); if (help_mode || ise) run("extractinv -inv INV O:I", "(only if '-ise')"); + run("clean"); } if (check_label("check")) { |