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Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc72
1 files changed, 49 insertions, 23 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b0c4795ee..5c3b5179d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -26,13 +26,16 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
- // to one LUT6 (instead of a LUT5 + LUT2)
-
struct SynthXilinxPass : public ScriptPass
{
SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
+ void on_register() YS_OVERRIDE
+ {
+ RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate
+ // to one LUT6 (instead of a LUT5 + LUT2)
+ }
+
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -107,8 +110,12 @@ struct SynthXilinxPass : public ScriptPass
log(" -flatten\n");
log(" flatten design before synthesis\n");
log("\n");
+ log(" -dff\n");
+ log(" run 'abc'/'abc9' with -dff option\n");
+ log("\n");
log(" -retime\n");
- log(" run 'abc' with '-dff -D 1' options\n");
+ log(" run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
+ log(" implies -dff.\n");
log("\n");
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
@@ -120,7 +127,8 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
- bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9;
+ bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
+ bool abc9, dff_mode;
bool flatten_before_abc;
int widemux;
@@ -145,6 +153,7 @@ struct SynthXilinxPass : public ScriptPass
nodsp = false;
uram = false;
abc9 = false;
+ dff_mode = false;
flatten_before_abc = false;
widemux = 0;
}
@@ -190,6 +199,7 @@ struct SynthXilinxPass : public ScriptPass
continue;
}
if (args[argidx] == "-retime") {
+ dff_mode = true;
retime = true;
continue;
}
@@ -252,6 +262,10 @@ struct SynthXilinxPass : public ScriptPass
uram = true;
continue;
}
+ if (args[argidx] == "-dff") {
+ dff_mode = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -287,10 +301,11 @@ struct SynthXilinxPass : public ScriptPass
ff_map_file = "+/xilinx/xc7_ff_map.v";
if (check_label("begin")) {
+ std::string read_args;
if (vpr)
- run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
- else
- run("read_verilog -lib +/xilinx/cells_sim.v");
+ read_args += " -D_EXPLICIT_CARRY";
+ read_args += " -lib +/xilinx/cells_sim.v";
+ run("read_verilog" + read_args);
run("read_verilog -lib +/xilinx/cells_xtra.v");
@@ -503,8 +518,6 @@ struct SynthXilinxPass : public ScriptPass
techmap_args += " -map +/xilinx/arith_map.v";
if (vpr)
techmap_args += " -D _EXPLICIT_CARRY";
- else if (abc9)
- techmap_args += " -D _CLB_CARRY";
}
run("techmap " + techmap_args);
run("opt -fast");
@@ -532,27 +545,42 @@ struct SynthXilinxPass : public ScriptPass
if (flatten_before_abc)
run("flatten");
if (help_mode)
- run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
+ run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')");
else if (abc9) {
if (family != "xc7")
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
- run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
+ std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1";
+ if (dff_mode)
+ techmap_args += " -D DFF_MODE";
+ run("techmap " + techmap_args);
run("read_verilog -icells -lib +/xilinx/abc9_model.v");
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
- abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
- abc9_opts += " -nomfs";
+ auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
+ if (active_design->scratchpad.count(k))
+ abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+ else
+ abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
if (nowidelut)
abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
else
abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
+ if (dff_mode)
+ abc9_opts += " -dff";
run("abc9" + abc9_opts);
+ run("techmap -map +/xilinx/abc9_unmap.v");
}
else {
+ std::string abc_opts;
if (nowidelut)
- run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
+ abc_opts += " -luts 2:2,3,6:5";
else
- run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
+ abc_opts += " -luts 2:2,3,6:5,10,20";
+ if (dff_mode)
+ abc_opts += " -dff";
+ if (retime)
+ abc_opts += " -D 1";
+ run("abc" + abc_opts);
}
run("clean");
@@ -562,14 +590,11 @@ struct SynthXilinxPass : public ScriptPass
run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
if (help_mode)
- techmap_args += " [-map " + ff_map_file + "]";
- else if (abc9)
- techmap_args += " -map +/xilinx/abc9_unmap.v";
- else
- techmap_args += " -map " + ff_map_file;
- run("techmap " + techmap_args);
+ techmap_args += stringf("[-map %s]", ff_map_file.c_str());
+ else if (!abc9)
+ techmap_args += stringf(" -map %s", ff_map_file.c_str());
+ run("techmap " + techmap_args, "(only if '-abc9')");
run("xilinx_dffopt");
- run("clean");
}
if (check_label("finalize")) {
@@ -577,6 +602,7 @@ struct SynthXilinxPass : public ScriptPass
run("clkbufmap -buf BUFG O:I ", "(skip if '-noclkbuf')");
if (help_mode || ise)
run("extractinv -inv INV O:I", "(only if '-ise')");
+ run("clean");
}
if (check_label("check")) {
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 03:27:43 +0000