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Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc119
1 files changed, 98 insertions, 21 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 8119d307c..a6b422b83 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -49,10 +49,25 @@ struct SynthXilinxPass : public ScriptPass
log(" -top <module>\n");
log(" use the specified module as top module\n");
log("\n");
- log(" -family {xcup|xcu|xc7|xc6v|xc5v|xc6s}\n");
+ log(" -family <family>\n");
log(" run synthesis for the specified Xilinx architecture\n");
log(" generate the synthesis netlist for the specified family.\n");
- log(" default: xc7\n");
+ log(" supported values:\n");
+ log(" - xcup: Ultrascale Plus\n");
+ log(" - xcu: Ultrascale\n");
+ log(" - xc7: Series 7 (default)\n");
+ log(" - xc6s: Spartan 6\n");
+ log(" - xc6v: Virtex 6\n");
+ log(" - xc5v: Virtex 5 (EXPERIMENTAL)\n");
+ log(" - xc4v: Virtex 4 (EXPERIMENTAL)\n");
+ log(" - xc3sda: Spartan 3A DSP (EXPERIMENTAL)\n");
+ log(" - xc3sa: Spartan 3A (EXPERIMENTAL)\n");
+ log(" - xc3se: Spartan 3E (EXPERIMENTAL)\n");
+ log(" - xc3s: Spartan 3 (EXPERIMENTAL)\n");
+ log(" - xc2vp: Virtex 2 Pro (EXPERIMENTAL)\n");
+ log(" - xc2v: Virtex 2 (EXPERIMENTAL)\n");
+ log(" - xcve: Virtex E, Spartan 2E (EXPERIMENTAL)\n");
+ log(" - xcv: Virtex, Spartan 2 (EXPERIMENTAL)\n");
log("\n");
log(" -edif <file>\n");
log(" write the design to the specified edif file. writing of an output file\n");
@@ -82,10 +97,10 @@ struct SynthXilinxPass : public ScriptPass
log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
log("\n");
log(" -nowidelut\n");
- log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
+ log(" do not use MUXF[5-9] resources to implement LUTs larger than native for the target\n");
log("\n");
log(" -nodsp\n");
- log(" do not use DSP48E1s to implement multipliers and associated logic\n");
+ log(" do not use DSP48*s to implement multipliers and associated logic\n");
log("\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (useful for hierarchical or \n");
@@ -131,6 +146,8 @@ struct SynthXilinxPass : public ScriptPass
bool abc9, dff_mode;
bool flatten_before_abc;
int widemux;
+ int lut_size;
+ int widelut_size;
void clear_flags() YS_OVERRIDE
{
@@ -156,6 +173,7 @@ struct SynthXilinxPass : public ScriptPass
dff_mode = false;
flatten_before_abc = false;
widemux = 0;
+ lut_size = 6;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -270,9 +288,38 @@ struct SynthXilinxPass : public ScriptPass
}
extra_args(args, argidx, design);
- if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc5v" && family != "xc6s")
+ if (family == "xcup" || family == "xcu") {
+ lut_size = 6;
+ widelut_size = 9;
+ } else if (family == "xc7" ||
+ family == "xc6v" ||
+ family == "xc5v" ||
+ family == "xc6s") {
+ lut_size = 6;
+ widelut_size = 8;
+ } else if (family == "xc4v" ||
+ family == "xc3sda" ||
+ family == "xc3sa" ||
+ family == "xc3se" ||
+ family == "xc3s" ||
+ family == "xc2vp" ||
+ family == "xc2v") {
+ lut_size = 4;
+ widelut_size = 8;
+ } else if (family == "xcve" || family == "xcv") {
+ lut_size = 4;
+ widelut_size = 6;
+ } else
log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
+ if (widemux != 0 && lut_size != 6)
+ log_cmd_error("-widemux is not currently supported for LUT4-based architectures.\n");
+
+ if (lut_size != 6) {
+ log_warning("Shift register inference not yet supported for family %s.\n", family.c_str());
+ nosrl = true;
+ }
+
if (widemux != 0 && widemux < 2)
log_cmd_error("-widemux value must be 0 or >= 2.\n");
@@ -292,6 +339,9 @@ struct SynthXilinxPass : public ScriptPass
void script() YS_OVERRIDE
{
+ std::string lut_size_s = std::to_string(lut_size);
+ if (help_mode)
+ lut_size_s = "[46]";
std::string ff_map_file;
if (help_mode)
ff_map_file = "+/xilinx/{family}_ff_map.v";
@@ -344,7 +394,7 @@ struct SynthXilinxPass : public ScriptPass
run("clean", " (skip if '-nosrl' and '-widemux=0')");
}
- run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
+ run("techmap -map +/cmp2lut.v -D LUT_WIDTH=" + lut_size_s);
}
if (check_label("map_dsp", "(skip if '-nodsp')")) {
@@ -353,7 +403,7 @@ struct SynthXilinxPass : public ScriptPass
// NB: Xilinx multipliers are signed only
if (help_mode)
run("techmap -map +/mul2dsp.v -map +/xilinx/{family}_dsp_map.v {options}");
- else if (family == "xc2v" || family == "xc3s" || family == "xc3se" || family == "xc3sa")
+ else if (family == "xc2v" || family == "xc2vp" || family == "xc3s" || family == "xc3se" || family == "xc3sa")
run("techmap -map +/mul2dsp.v -map +/xilinx/xc3s_mult_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
@@ -438,7 +488,19 @@ struct SynthXilinxPass : public ScriptPass
run("memory_bram -rules +/xilinx/{family}_brams.txt");
run("techmap -map +/xilinx/{family}_brams_map.v");
} else if (!nobram) {
- if (family == "xc6s") {
+ if (family == "xc2v" || family == "xc2vp" || family == "xc3s" || family == "xc3se") {
+ run("memory_bram -rules +/xilinx/xc2v_brams.txt");
+ run("techmap -map +/xilinx/xc2v_brams_map.v");
+ } else if (family == "xc3sa") {
+ // Superset of Virtex 2 primitives — uses common map file.
+ run("memory_bram -rules +/xilinx/xc3sa_brams.txt");
+ run("techmap -map +/xilinx/xc2v_brams_map.v");
+ } else if (family == "xc3sda") {
+ // Supported block RAMs for Spartan 3A DSP are
+ // a subset of Spartan 6's ones.
+ run("memory_bram -rules +/xilinx/xc3sda_brams.txt");
+ run("techmap -map +/xilinx/xc6s_brams_map.v");
+ } else if (family == "xc6s") {
run("memory_bram -rules +/xilinx/xc6s_brams.txt");
run("techmap -map +/xilinx/xc6s_brams_map.v");
} else if (family == "xc6v" || family == "xc7") {
@@ -455,7 +517,7 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_lutram", "(skip if '-nolutram')")) {
if (!nolutram || help_mode) {
- run("memory_bram -rules +/xilinx/lutrams.txt");
+ run("memory_bram -rules +/xilinx/lut" + lut_size_s + "_lutrams.txt");
run("techmap -map +/xilinx/lutrams_map.v");
}
}
@@ -481,9 +543,8 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("fine")) {
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
- if (help_mode) {
- run("muxcover <internal options>, ('-widemux' only)");
- }
+ if (help_mode)
+ run("muxcover <internal options> ('-widemux' only)");
else if (widemux > 0) {
constexpr int cost_mux2 = 100;
std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
@@ -511,14 +572,12 @@ struct SynthXilinxPass : public ScriptPass
if (!nosrl || help_mode)
run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')");
- std::string techmap_args = " -map +/techmap.v";
+ std::string techmap_args = " -map +/techmap.v -D LUT_SIZE=" + lut_size_s;
if (help_mode)
techmap_args += " [-map +/xilinx/mux_map.v]";
else if (widemux > 0)
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
- if (help_mode)
- techmap_args += " [-map +/xilinx/arith_map.v]";
- else if (!nocarry) {
+ if (!nocarry) {
techmap_args += " -map +/xilinx/arith_map.v";
if (vpr)
techmap_args += " -D _EXPLICIT_CARRY";
@@ -551,6 +610,8 @@ struct SynthXilinxPass : public ScriptPass
if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')");
else if (abc9) {
+ if (lut_size != 6)
+ log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n");
if (family != "xc7")
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
@@ -576,10 +637,19 @@ struct SynthXilinxPass : public ScriptPass
}
else {
std::string abc_opts;
- if (nowidelut)
- abc_opts += " -luts 2:2,3,6:5";
- else
- abc_opts += " -luts 2:2,3,6:5,10,20";
+ if (lut_size != 6) {
+ if (nowidelut)
+ abc_opts += " -lut " + lut_size_s;
+ else
+ abc_opts += " -lut " + lut_size_s + ":" + std::to_string(widelut_size);
+ } else {
+ if (nowidelut)
+ abc_opts += " -luts 2:2,3,6:5";
+ else if (widelut_size == 8)
+ abc_opts += " -luts 2:2,3,6:5,10,20";
+ else
+ abc_opts += " -luts 2:2,3,6:5,10,20,40";
+ }
if (dff_mode)
abc_opts += " -dff";
if (retime)
@@ -595,8 +665,15 @@ struct SynthXilinxPass : public ScriptPass
std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
if (help_mode || !abc9)
techmap_args += stringf(" -map %s", ff_map_file.c_str());
+ techmap_args += " -D LUT_WIDTH=" + lut_size_s;
run("techmap " + techmap_args);
- run("xilinx_dffopt");
+ if (help_mode)
+ run("xilinx_dffopt [-lut4]");
+ else if (lut_size == 4)
+ run("xilinx_dffopt -lut4");
+ else
+ run("xilinx_dffopt");
+ run("opt_lut_ins -tech xilinx");
}
if (check_label("finalize")) {
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 15:58:33 +0000