diff options
Diffstat (limited to 'techlibs/xilinx/xc7_ff_map.v')
| -rw-r--r-- | techlibs/xilinx/xc7_ff_map.v | 40 |
1 files changed, 39 insertions, 1 deletions
diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v index f6197b78b..32ca9f560 100644 --- a/techlibs/xilinx/xc7_ff_map.v +++ b/techlibs/xilinx/xc7_ff_map.v @@ -18,60 +18,98 @@ */ // ============================================================================ -// FF mapping +// FF mapping for Virtex 6, Series 7 and Ultrascale. These families support +// the following features: +// +// - a CLB flip-flop can be used as a latch or as a flip-flop +// - a CLB flip-flop has the following pins: +// +// - data input +// - clock (or gate for latches) (with optional inversion) +// - clock enable (or gate enable, which is just ANDed with gate — unused by +// synthesis) +// - either a set or a reset input, which (for FFs) can be either +// synchronous or asynchronous (with optional inversion) +// - data output +// +// - a flip-flop also has an initial value, which is set at device +// initialization (or whenever GSR is asserted) `ifndef _NO_FFS module \$_DFF_N_ (input D, C, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_P_ (input D, C, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFFE_NP_ (input D, C, E, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFFE_PP_ (input D, C, E, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_NN0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_NP0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_PN0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_PP0_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_NN1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_NP1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_PN1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_PP1_ (input D, C, R, output Q); parameter _TECHMAP_WIREINIT_Q_ = 1'bx; FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$_DLATCH_N_ (input E, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_P_ (input E, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule `endif |