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-rw-r--r--techlibs/xilinx/synth_xilinx.cc10
1 files changed, 9 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 53eee7962..5820d6d61 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -83,6 +83,9 @@ struct SynthXilinxPass : public Pass
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log("\n");
+ log(" -abc9\n");
+ log(" use abc9 instead of abc\n");
+ log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
log("\n");
@@ -152,6 +155,7 @@ struct SynthXilinxPass : public Pass
std::string edif_file;
std::string blif_file;
std::string run_from, run_to;
+ std::string abc = "abc";
bool flatten = false;
bool retime = false;
bool vpr = false;
@@ -205,6 +209,10 @@ struct SynthXilinxPass : public Pass
if (args[argidx] == "-nosrl") {
nosrl = true;
continue;
+ }
+ if (args[argidx] == "-abc9") {
+ abc = "abc9";
+ continue;
}
break;
}
@@ -304,7 +312,7 @@ struct SynthXilinxPass : public Pass
{
Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
- Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+ Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");
// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming