aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r--techlibs/xilinx/cells_sim.v34
-rw-r--r--techlibs/xilinx/cells_xtra.py5
-rw-r--r--techlibs/xilinx/cells_xtra.v43
-rw-r--r--techlibs/xilinx/lut_map.v8
4 files changed, 62 insertions, 28 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 5faddcd52..1be43f9d4 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -59,6 +59,34 @@ module OBUF(
assign O = I;
endmodule
+module IOBUF (
+ (* iopad_external_pin *)
+ inout IO,
+ output O,
+ input I,
+ input T
+);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ assign IO = T ? 1'bz : I;
+ assign O = IO;
+endmodule
+
+module OBUFT (
+ (* iopad_external_pin *)
+ output O,
+ input I,
+ input T
+);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter integer DRIVE = 12;
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ assign O = T ? 1'bz : I;
+endmodule
+
module BUFG(
(* clkbuf_driver *)
output O,
@@ -126,7 +154,11 @@ endmodule
// assign O = IO, IO = T ? 1'bz : I;
// endmodule
-module INV(output O, input I);
+module INV(
+ (* clkbuf_inv = "I" *)
+ output O,
+ input I
+);
assign O = !I;
endmodule
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index f401ebe78..01e7101d1 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -326,7 +326,7 @@ CELLS = [
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
# I/O.
- Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+ # Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
@@ -342,7 +342,7 @@ CELLS = [
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
# Output + tristate.
- Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+ # Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
# Pulls.
Cell('KEEPER'),
@@ -372,6 +372,7 @@ CELLS = [
Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}),
Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}),
# Clock buffers (IO and regional) -- Virtex.
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index ce0949f2c..00a8a5f8a 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -5240,9 +5240,13 @@ module RAMB18E1 (...);
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
+ (* abc9_arrival=2454 *)
output [15:0] DOADO;
+ (* abc9_arrival=2454 *)
output [15:0] DOBDO;
+ (* abc9_arrival=2454 *)
output [1:0] DOPADOP;
+ (* abc9_arrival=2454 *)
output [1:0] DOPBDOP;
(* clkbuf_sink *)
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
@@ -5452,9 +5456,13 @@ module RAMB36E1 (...);
parameter IS_RSTREGB_INVERTED = 1'b0;
output CASCADEOUTA;
output CASCADEOUTB;
+ (* abc9_arrival=2454 *)
output [31:0] DOADO;
+ (* abc9_arrival=2454 *)
output [31:0] DOBDO;
+ (* abc9_arrival=2454 *)
output [3:0] DOPADOP;
+ (* abc9_arrival=2454 *)
output [3:0] DOPBDOP;
output [7:0] ECCPARITY;
output [8:0] RDADDRECC;
@@ -8160,18 +8168,6 @@ module IBUFGDS_DIFF_OUT (...);
input IB;
endmodule
-module IOBUF (...);
- parameter integer DRIVE = 12;
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SLEW = "SLOW";
- output O;
- (* iopad_external_pin *)
- inout IO;
- input I;
- input T;
-endmodule
-
module IOBUF_DCIEN (...);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
@@ -8373,17 +8369,6 @@ module OBUFDS_DPHY (...);
input LPTX_T;
endmodule
-module OBUFT (...);
- parameter CAPACITANCE = "DONT_CARE";
- parameter integer DRIVE = 12;
- parameter IOSTANDARD = "DEFAULT";
- parameter SLEW = "SLOW";
- (* iopad_external_pin *)
- output O;
- input I;
- input T;
-endmodule
-
module OBUFTDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
@@ -8550,6 +8535,18 @@ module BUFIO2FB (...);
input I;
endmodule
+module BUFPLL (...);
+ parameter integer DIVIDE = 1;
+ parameter ENABLE_SYNC = "TRUE";
+ (* clkbuf_driver *)
+ output IOCLK;
+ output LOCK;
+ output SERDESSTROBE;
+ input GCLK;
+ input LOCKED;
+ input PLLIN;
+endmodule
+
module BUFPLL_MCB (...);
parameter integer DIVIDE = 2;
parameter LOCK_SRC = "LOCK_TO_0";
diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v
index 13d3c3268..62d501632 100644
--- a/techlibs/xilinx/lut_map.v
+++ b/techlibs/xilinx/lut_map.v
@@ -56,8 +56,12 @@ module \$lut (A, Y);
generate
if (WIDTH == 1) begin
- LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]));
+ if (P_LUT == 2'b01) begin
+ INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0]));
+ end else begin
+ LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I0(A[0]));
+ end
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 08:30:54 +0000