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-rw-r--r--techlibs/xilinx/Makefile.inc2
-rw-r--r--techlibs/xilinx/brams.txt14
-rw-r--r--techlibs/xilinx/brams_init.py5
-rw-r--r--techlibs/xilinx/brams_map.v24
-rw-r--r--techlibs/xilinx/example_basys3/README16
-rw-r--r--techlibs/xilinx/example_basys3/example.v21
-rw-r--r--techlibs/xilinx/example_basys3/example.xdc21
-rw-r--r--techlibs/xilinx/example_basys3/run.sh4
-rw-r--r--techlibs/xilinx/example_basys3/run_prog.tcl4
-rw-r--r--techlibs/xilinx/example_basys3/run_vivado.tcl9
-rw-r--r--techlibs/xilinx/example_basys3/run_yosys.ys2
-rw-r--r--techlibs/xilinx/synth_xilinx.cc6
12 files changed, 26 insertions, 102 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index cca41f917..ccf88ec7e 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -11,7 +11,7 @@ EXTRA_OBJS += techlibs/xilinx/brams_init.mk
techlibs/xilinx/brams_init.mk: techlibs/xilinx/brams_init.py
$(Q) mkdir -p techlibs/xilinx
- $(P) python $<
+ $(P) python3 $<
$(Q) touch $@
techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk
diff --git a/techlibs/xilinx/brams.txt b/techlibs/xilinx/brams.txt
index 894e714c6..f1161114e 100644
--- a/techlibs/xilinx/brams.txt
+++ b/techlibs/xilinx/brams.txt
@@ -6,7 +6,7 @@ bram $__XILINX_RAMB36_SDP
groups 2
ports 1 1
wrmode 0 1
- enable 0 8
+ enable 1 8
transp 0 0
clocks 2 3
clkpol 2 3
@@ -19,7 +19,7 @@ bram $__XILINX_RAMB18_SDP
groups 2
ports 1 1
wrmode 0 1
- enable 0 4
+ enable 1 4
transp 0 0
clocks 2 3
clkpol 2 3
@@ -42,9 +42,9 @@ bram $__XILINX_RAMB36_TDP
groups 2
ports 1 1
wrmode 0 1
- enable 0 4 @a10d36
- enable 0 2 @a11d18
- enable 0 1 @a12d9 @a13d4 @a14d2 @a15d1
+ enable 1 4 @a10d36
+ enable 1 2 @a11d18
+ enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1
transp 0 0
clocks 2 3
clkpol 2 3
@@ -65,8 +65,8 @@ bram $__XILINX_RAMB18_TDP
groups 2
ports 1 1
wrmode 0 1
- enable 0 2 @a10d18
- enable 0 1 @a11d9 @a12d4 @a13d2 @a14d1
+ enable 1 2 @a10d18
+ enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
transp 0 0
clocks 2 3
clkpol 2 3
diff --git a/techlibs/xilinx/brams_init.py b/techlibs/xilinx/brams_init.py
index eac829ddf..e787b1f76 100644
--- a/techlibs/xilinx/brams_init.py
+++ b/techlibs/xilinx/brams_init.py
@@ -1,7 +1,4 @@
-#!/usr/bin/python
-
-from __future__ import division
-from __future__ import print_function
+#!/usr/bin/env python3
with open("techlibs/xilinx/brams_init_18.vh", "w") as f:
for i in range(8):
diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v
index cbfd4e1eb..7ea49158d 100644
--- a/techlibs/xilinx/brams_map.v
+++ b/techlibs/xilinx/brams_map.v
@@ -1,4 +1,4 @@
-module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [36863:0] INIT = 36864'bx;
@@ -8,6 +8,7 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
input [8:0] A1ADDR;
output [71:0] A1DATA;
+ input A1EN;
input [8:0] B1ADDR;
input [71:0] B1DATA;
@@ -47,7 +48,7 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
- .ENARDEN(|1),
+ .ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
@@ -65,7 +66,7 @@ endmodule
// ------------------------------------------------------------------------
-module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
@@ -75,6 +76,7 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
input [8:0] A1ADDR;
output [35:0] A1DATA;
+ input A1EN;
input [8:0] B1ADDR;
input [35:0] B1DATA;
@@ -111,7 +113,7 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
- .ENARDEN(|1),
+ .ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
@@ -129,7 +131,7 @@ endmodule
// ------------------------------------------------------------------------
-module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
@@ -143,6 +145,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
+ input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
@@ -181,7 +184,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.DOPADOP(DOP[3:0]),
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
- .ENARDEN(|1),
+ .ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
@@ -219,7 +222,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.DOPADOP(DOP[3:0]),
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
- .ENARDEN(|1),
+ .ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
@@ -242,7 +245,7 @@ endmodule
// ------------------------------------------------------------------------
-module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_B = 2;
@@ -256,6 +259,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
+ input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
@@ -294,7 +298,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
- .ENARDEN(|1),
+ .ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
@@ -332,7 +336,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
- .ENARDEN(|1),
+ .ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
diff --git a/techlibs/xilinx/example_basys3/README b/techlibs/xilinx/example_basys3/README
deleted file mode 100644
index 85b6eab10..000000000
--- a/techlibs/xilinx/example_basys3/README
+++ /dev/null
@@ -1,16 +0,0 @@
-
-A simple example design, based on the Digilent BASYS3 board
-===========================================================
-
-Running Yosys:
- yosys run_yosys.ys
-
-Running Vivado:
- vivado -nolog -nojournal -mode batch -source run_vivado.tcl
-
-Programming board:
- vivado -nolog -nojournal -mode batch -source run_prog.tcl
-
-All of the above:
- bash run.sh
-
diff --git a/techlibs/xilinx/example_basys3/example.v b/techlibs/xilinx/example_basys3/example.v
deleted file mode 100644
index 2b01a22a8..000000000
--- a/techlibs/xilinx/example_basys3/example.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module example(CLK, LD);
- input CLK;
- output [15:0] LD;
-
- wire clock;
- reg [15:0] leds;
-
- BUFG CLK_BUF (.I(CLK), .O(clock));
- OBUF LD_BUF[15:0] (.I(leds), .O(LD));
-
- parameter COUNTBITS = 26;
- reg [COUNTBITS-1:0] counter;
-
- always @(posedge CLK) begin
- counter <= counter + 1;
- if (counter[COUNTBITS-1])
- leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
- else
- leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
- end
-endmodule
diff --git a/techlibs/xilinx/example_basys3/example.xdc b/techlibs/xilinx/example_basys3/example.xdc
deleted file mode 100644
index c1fd0e925..000000000
--- a/techlibs/xilinx/example_basys3/example.xdc
+++ /dev/null
@@ -1,21 +0,0 @@
-
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W5 } [get_ports CLK]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U16 } [get_ports {LD[0]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN E19 } [get_ports {LD[1]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U19 } [get_ports {LD[2]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V19 } [get_ports {LD[3]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W18 } [get_ports {LD[4]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U15 } [get_ports {LD[5]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U14 } [get_ports {LD[6]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V14 } [get_ports {LD[7]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V13 } [get_ports {LD[8]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V3 } [get_ports {LD[9]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W3 } [get_ports {LD[10]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U3 } [get_ports {LD[11]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P3 } [get_ports {LD[12]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN N3 } [get_ports {LD[13]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P1 } [get_ports {LD[14]}]
-set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1 } [get_ports {LD[15]}]
-
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
-
diff --git a/techlibs/xilinx/example_basys3/run.sh b/techlibs/xilinx/example_basys3/run.sh
deleted file mode 100644
index 10f059103..000000000
--- a/techlibs/xilinx/example_basys3/run.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/bash
-yosys run_yosys.ys
-vivado -nolog -nojournal -mode batch -source run_vivado.tcl
-vivado -nolog -nojournal -mode batch -source run_prog.tcl
diff --git a/techlibs/xilinx/example_basys3/run_prog.tcl b/techlibs/xilinx/example_basys3/run_prog.tcl
deleted file mode 100644
index d711af840..000000000
--- a/techlibs/xilinx/example_basys3/run_prog.tcl
+++ /dev/null
@@ -1,4 +0,0 @@
-connect_hw_server
-open_hw_target [lindex [get_hw_targets] 0]
-set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0]
-program_hw_devices [lindex [get_hw_devices] 0]
diff --git a/techlibs/xilinx/example_basys3/run_vivado.tcl b/techlibs/xilinx/example_basys3/run_vivado.tcl
deleted file mode 100644
index c3b6a610e..000000000
--- a/techlibs/xilinx/example_basys3/run_vivado.tcl
+++ /dev/null
@@ -1,9 +0,0 @@
-read_xdc example.xdc
-read_edif example.edif
-link_design -part xc7a35tcpg236-1 -top example
-opt_design
-place_design
-route_design
-report_utilization
-report_timing
-write_bitstream -force example.bit
diff --git a/techlibs/xilinx/example_basys3/run_yosys.ys b/techlibs/xilinx/example_basys3/run_yosys.ys
deleted file mode 100644
index 4541826d3..000000000
--- a/techlibs/xilinx/example_basys3/run_yosys.ys
+++ /dev/null
@@ -1,2 +0,0 @@
-read_verilog example.v
-synth_xilinx -edif example.edif -top example
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b3d4c214f..fbcc96014 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -79,7 +79,6 @@ struct SynthXilinxPass : public Pass {
log("\n");
log(" coarse:\n");
log(" synth -run coarse\n");
- log(" dff2dffe\n");
log("\n");
log(" bram:\n");
log(" memory_bram -rules +/xilinx/brams.txt\n");
@@ -92,6 +91,7 @@ struct SynthXilinxPass : public Pass {
log(" fine:\n");
log(" opt -fast -full\n");
log(" memory_map\n");
+ log(" dff2dffe\n");
log(" opt -full\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
log(" opt -fast\n");
@@ -178,7 +178,6 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "coarse"))
{
Pass::call(design, "synth -run coarse");
- Pass::call(design, "dff2dffe");
}
if (check_label(active, run_from, run_to, "bram"))
@@ -197,6 +196,7 @@ struct SynthXilinxPass : public Pass {
{
Pass::call(design, "opt -fast -full");
Pass::call(design, "memory_map");
+ Pass::call(design, "dff2dffe");
Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
Pass::call(design, "opt -fast");
@@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_luts"))
{
- Pass::call(design, "abc -lut 5:8" + string(retime ? " -dff" : ""));
+ Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-24 12:18:34 +0000