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-rw-r--r--techlibs/xilinx/abc9_map.v225
-rw-r--r--techlibs/xilinx/abc9_model.v7
-rw-r--r--techlibs/xilinx/abc9_unmap.v8
-rw-r--r--techlibs/xilinx/abc9_xc7.box51
-rw-r--r--techlibs/xilinx/cells_sim.v124
-rw-r--r--techlibs/xilinx/cells_xtra.py4
-rw-r--r--techlibs/xilinx/cells_xtra.v23
-rw-r--r--techlibs/xilinx/lut_map.v8
-rw-r--r--techlibs/xilinx/synth_xilinx.cc14
9 files changed, 389 insertions, 75 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 0eac08f3f..29ddf7133 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -18,7 +18,230 @@
*
*/
-// ============================================================================
+// The following techmapping rules are intended to be run (with -max_iter 1)
+// before invoking the `abc9` pass in order to transform the design into
+// a format that it understands.
+//
+// For example, (complex) flip-flops are expected to be described as an
+// combinatorial box (containing all control logic such as clock enable
+// or synchronous resets) followed by a basic D-Q flop.
+// Yosys will automatically analyse the simulation model (described in
+// cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
+// order to extract the combinatorial control logic left behind.
+// Specifically, a simulation model similar to the one below:
+//
+// ++===================================++
+// || Sim model ||
+// || /\/\/\/\ ||
+// D -->>-----< > +------+ ||
+// R -->>-----< Comb. > |$_DFF_| ||
+// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q
+// || +--< > +------+ | ||
+// || | \/\/\/\/ | ||
+// || | | ||
+// || +----------------------------+ ||
+// || ||
+// ++===================================++
+//
+// is transformed into:
+//
+// ++==================++
+// || Comb box ||
+// || ||
+// || /\/\/\/\ ||
+// D -->>-----< > || +------+
+// R -->>-----< Comb. > || |$__ABC|
+// CE -->>-----< logic >--->>-- $nextQ --| _FF_ |--+-->> Q
+// $abc9_currQ +-->>-----< > || +------+ |
+// | || \/\/\/\/ || |
+// | || || |
+// | ++==================++ |
+// | |
+// +----------------------------------------------+
+//
+// The purpose of the following FD* rules are to wrap the flop with:
+// (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
+// the connectivity of its basic D-Q flop
+// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to indicate its clock
+// signal, used to extract the delay target
+// (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control
+// domain (which, combined with this cell type, encodes to `abc9' which
+// flops may be merged together)
+// (d) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
+// into the (combinatorial) FD* cell to facilitate clock-enable behaviour
+module FDRE (output reg Q, input C, CE, D, R);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_R_INVERTED = 1'b0;
+ wire $nextQ;
+ FDRE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_R_INVERTED(IS_R_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+ );
+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+ // Special signals
+ wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+ wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+ parameter [0:0] INIT = 1'b0;
+ wire $nextQ;
+ FDRE_1 #(
+ .INIT(INIT),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+ );
+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+ // Special signals
+ wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+ wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ wire $nextQ, $abc9_currQ;
+ FDCE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_CLR_INVERTED(IS_CLR_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+ // ^^^ Note that async
+ // control is not directly
+ // supported by abc9 but its
+ // behaviour is captured by
+ // $__ABC9_ASYNC below
+ );
+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC9_ASYNC box by abc9_map.v
+ \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+
+ // Special signals
+ wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+ wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+ parameter [0:0] INIT = 1'b0;
+ wire $nextQ, $abc9_currQ;
+ FDCE_1 #(
+ .INIT(INIT)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+ // ^^^ Note that async
+ // control is not directly
+ // supported by abc9 but its
+ // behaviour is captured by
+ // $__ABC9_ASYNC below
+ );
+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+ \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q));
+
+ // Special signals
+ wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+ wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ wire $nextQ, $abc9_currQ;
+ FDPE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_PRE_INVERTED(IS_PRE_INVERTED),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+ // ^^^ Note that async
+ // control is not directly
+ // supported by abc9 but its
+ // behaviour is captured by
+ // $__ABC9_ASYNC below
+ );
+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+ \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+
+ // Special signals
+ wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+ wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
+ parameter [0:0] INIT = 1'b0;
+ wire $nextQ, $abc9_currQ;
+ FDPE_1 #(
+ .INIT(INIT)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+ // ^^^ Note that async
+ // control is not directly
+ // supported by abc9 but its
+ // behaviour is captured by
+ // $__ABC9_ASYNC below
+ );
+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+ \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q));
+
+ // Special signals
+ wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+ wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+endmodule
+
+module FDSE (output reg Q, input C, CE, D, S);
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_S_INVERTED = 1'b0;
+ wire $nextQ;
+ FDSE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_S_INVERTED(IS_S_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+ );
+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+ // Special signals
+ wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+ wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
+endmodule
+module FDSE_1 (output reg Q, input C, CE, D, S);
+ parameter [0:0] INIT = 1'b1;
+ wire $nextQ;
+ FDSE_1 #(
+ .INIT(INIT),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+ );
+ \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+ // Special signals
+ wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+ wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+ wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
+endmodule
module RAM32X1D (
output DPO, SPO,
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 8c8e1556c..cc0e5ec41 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -30,6 +30,13 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
: (S0 ? I1 : I0);
endmodule
+module \$__ABC9_FF_ (input D, output Q);
+endmodule
+
+(* abc_box_id = 1000 *)
+module \$__ABC9_ASYNC (input A, S, output Y);
+endmodule
+
// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
// Necessary since RAMD* and SRL* have both combinatorial (i.e.
// same-cycle read operation) and sequential (write operation
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v
index ad6469702..21fe78d08 100644
--- a/techlibs/xilinx/abc9_unmap.v
+++ b/techlibs/xilinx/abc9_unmap.v
@@ -20,6 +20,14 @@
// ============================================================================
+module \$__ABC9_ASYNC (input A, S, output Y);
+ assign Y = A;
+endmodule
+
+module \$__ABC9_FF_ (input D, output Q);
+ assign Q = D;
+endmodule
+
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
assign Y = A;
endmodule
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 774388d49..24b1898a4 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -41,6 +41,57 @@ CARRY4 4 1 10 8
592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114
+# Box to emulate async behaviour of FD[CP]*
+# Inputs: A S
+# Outputs: Y
+$__ABC9_ASYNC 1000 0 2 1
+0 764
+
+# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
+# reflect the -46ps Tsu
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+
+# Inputs: C CE D R \$currQ
+# Outputs: Q
+FDRE 1001 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE D R \$currQ
+# Outputs: Q
+FDRE_1 1002 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE CLR D \$currQ
+# Outputs: Q
+FDCE 1003 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE CLR D \$currQ
+# Outputs: Q
+FDCE_1 1004 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE D PRE \$currQ
+# Outputs: Q
+FDPE 1005 1 5 1
+0 151 0 806 0
+
+# Inputs: C CE D PRE \$currQ
+# Outputs: Q
+FDPE_1 1006 1 5 1
+0 151 0 806 0
+
+# Inputs: C CE D S \$currQ
+# Outputs: Q
+FDSE 1007 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE D S \$currQ
+# Outputs: Q
+FDSE_1 1008 1 5 1
+0 151 0 446 0
+
# SLICEM/A6LUT
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
# Necessary since RAMD* and SRL* have both combinatorial (i.e.
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 5faddcd52..d845b324f 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -59,6 +59,34 @@ module OBUF(
assign O = I;
endmodule
+module IOBUF (
+ (* iopad_external_pin *)
+ inout IO,
+ output O,
+ input I,
+ input T
+);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ assign IO = T ? 1'bz : I;
+ assign O = IO;
+endmodule
+
+module OBUFT (
+ (* iopad_external_pin *)
+ output O,
+ input I,
+ input T
+);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter integer DRIVE = 12;
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ assign O = T ? 1'bz : I;
+endmodule
+
module BUFG(
(* clkbuf_driver *)
output O,
@@ -126,7 +154,11 @@ endmodule
// assign O = IO, IO = T ? 1'bz : I;
// endmodule
-module INV(output O, input I);
+module INV(
+ (* clkbuf_inv = "I" *)
+ output O,
+ input I
+);
assign O = !I;
endmodule
@@ -251,6 +283,7 @@ endmodule
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
+(* abc9_box_id=1001, lib_whitebox, abc9_flop *)
module FDRE (
(* abc9_arrival=303 *)
output reg Q,
@@ -274,29 +307,20 @@ module FDRE (
endcase endgenerate
endmodule
-module FDSE (
+(* abc9_box_id=1002, lib_whitebox, abc9_flop *)
+module FDRE_1 (
(* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
- (* invertible_pin = "IS_C_INVERTED" *)
input C,
- input CE,
- (* invertible_pin = "IS_D_INVERTED" *)
- input D,
- (* invertible_pin = "IS_S_INVERTED" *)
- input S
+ input CE, D, R
);
- parameter [0:0] INIT = 1'b1;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_S_INVERTED = 1'b0;
+ parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
- generate case (|IS_C_INVERTED)
- 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- endcase endgenerate
+ always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
endmodule
+(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
module FDCE (
(* abc9_arrival=303 *)
output reg Q,
@@ -322,6 +346,20 @@ module FDCE (
endcase endgenerate
endmodule
+(* abc9_box_id=1004, lib_whitebox, abc9_flop *)
+module FDCE_1 (
+ (* abc9_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, CLR
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q <= INIT;
+ always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+endmodule
+
+(* abc9_box_id=1005, lib_whitebox, abc9_flop *)
module FDPE (
(* abc9_arrival=303 *)
output reg Q,
@@ -340,59 +378,61 @@ module FDPE (
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
- 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
+ 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
+ 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
+ 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
endcase endgenerate
endmodule
-module FDRE_1 (
- (* abc9_arrival=303 *)
- output reg Q,
- (* clkbuf_sink *)
- input C,
- input CE, D, R
-);
- parameter [0:0] INIT = 1'b0;
- initial Q <= INIT;
- always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
-endmodule
-
-module FDSE_1 (
+(* abc9_box_id=1006, lib_whitebox, abc9_flop *)
+module FDPE_1 (
(* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
- input CE, D, S
+ input CE, D, PRE
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
- always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
+ always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
-module FDCE_1 (
+(* abc9_box_id=1007, lib_whitebox, abc9_flop *)
+module FDSE (
(* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
input C,
- input CE, D, CLR
+ input CE,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_S_INVERTED" *)
+ input S
);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
- always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+ generate case (|IS_C_INVERTED)
+ 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+ endcase endgenerate
endmodule
-module FDPE_1 (
+(* abc9_box_id=1008, lib_whitebox, abc9_flop *)
+module FDSE_1 (
(* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
- input CE, D, PRE
+ input CE, D, S
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
- always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+ always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
endmodule
module LDCE (
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index f401ebe78..82e403f78 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -326,7 +326,7 @@ CELLS = [
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
# I/O.
- Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+ # Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
@@ -342,7 +342,7 @@ CELLS = [
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
# Output + tristate.
- Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+ # Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
# Pulls.
Cell('KEEPER'),
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index ce0949f2c..671d16e8a 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -8160,18 +8160,6 @@ module IBUFGDS_DIFF_OUT (...);
input IB;
endmodule
-module IOBUF (...);
- parameter integer DRIVE = 12;
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SLEW = "SLOW";
- output O;
- (* iopad_external_pin *)
- inout IO;
- input I;
- input T;
-endmodule
-
module IOBUF_DCIEN (...);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
@@ -8373,17 +8361,6 @@ module OBUFDS_DPHY (...);
input LPTX_T;
endmodule
-module OBUFT (...);
- parameter CAPACITANCE = "DONT_CARE";
- parameter integer DRIVE = 12;
- parameter IOSTANDARD = "DEFAULT";
- parameter SLEW = "SLOW";
- (* iopad_external_pin *)
- output O;
- input I;
- input T;
-endmodule
-
module OBUFTDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v
index 13d3c3268..62d501632 100644
--- a/techlibs/xilinx/lut_map.v
+++ b/techlibs/xilinx/lut_map.v
@@ -56,8 +56,12 @@ module \$lut (A, Y);
generate
if (WIDTH == 1) begin
- LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
- .I0(A[0]));
+ if (P_LUT == 2'b01) begin
+ INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0]));
+ end else begin
+ LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I0(A[0]));
+ end
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3d4a65c5d..5bc55387b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -291,10 +291,11 @@ struct SynthXilinxPass : public ScriptPass
ff_map_file = "+/xilinx/xc7_ff_map.v";
if (check_label("begin")) {
+ std::string read_args;
if (vpr)
- run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
- else
- run("read_verilog -lib +/xilinx/cells_sim.v");
+ read_args += " -D_EXPLICIT_CARRY";
+ read_args += " -lib +/xilinx/cells_sim.v";
+ run("read_verilog" + read_args);
run("read_verilog -lib +/xilinx/cells_xtra.v");
@@ -512,6 +513,7 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_ffs")) {
if (abc9 || help_mode) {
+ run("clkpart -set_attr clkpart 1", "('-abc9' only)");
run("techmap -map " + ff_map_file, "('-abc9' only)");
}
}
@@ -536,14 +538,16 @@ struct SynthXilinxPass : public ScriptPass
else
abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
run("abc9" + abc9_opts);
+ run("clean");
+ run("clkpart -unpart clkpart");
}
else {
if (nowidelut)
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
else
run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+ run("clean");
}
- run("clean");
// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming
@@ -557,7 +561,6 @@ struct SynthXilinxPass : public ScriptPass
else
techmap_args += " -map " + ff_map_file;
run("techmap " + techmap_args);
- run("clean");
}
if (check_label("finalize")) {
@@ -572,6 +575,7 @@ struct SynthXilinxPass : public ScriptPass
run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
if (help_mode || ise)
run("extractinv -inv INV O:I", "(only if '-ise')");
+ run("clean");
}
if (check_label("check")) {
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 20:31:24 +0000