diff options
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 3 | ||||
| -rw-r--r-- | techlibs/xilinx/arith_map.v | 114 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 37 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 108 | ||||
| -rw-r--r-- | techlibs/xilinx/ff_map.v | 120 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 77 | ||||
| -rw-r--r-- | techlibs/xilinx/xc6s_ff_map.v | 256 | ||||
| -rw-r--r-- | techlibs/xilinx/xc7_dsp_map.v | 1 | ||||
| -rw-r--r-- | techlibs/xilinx/xc7_ff_map.v | 178 | ||||
| -rw-r--r-- | techlibs/xilinx/xilinx_dffopt.cc | 4 |
10 files changed, 219 insertions, 679 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index d4d863831..ba87278de 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -42,8 +42,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut4_lutrams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut6_lutrams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v)) diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 2fc216908..eb8a04bde 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -35,13 +35,7 @@ module _80_xilinx_lcu (P, G, CI, CO); genvar i; -`ifdef _EXPLICIT_CARRY - localparam EXPLICIT_CARRY = 1'b1; -`else - localparam EXPLICIT_CARRY = 1'b0; -`endif - -generate if (EXPLICIT_CARRY || `LUT_SIZE == 4) begin +generate if (`LUT_SIZE == 4) begin (* force_downto *) wire [WIDTH-1:0] C = {CO, CI}; @@ -135,12 +129,6 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); genvar i; -`ifdef _EXPLICIT_CARRY - localparam EXPLICIT_CARRY = 1'b1; -`else - localparam EXPLICIT_CARRY = 1'b0; -`endif - generate if (`LUT_SIZE == 4) begin (* force_downto *) @@ -163,106 +151,6 @@ generate if (`LUT_SIZE == 4) begin ); end endgenerate -end else if (EXPLICIT_CARRY) begin - - (* force_downto *) - wire [Y_WIDTH-1:0] S = AA ^ BB; - - wire CINIT; - // Carry chain. - // - // VPR requires that the carry chain never hit the fabric. The CO input - // to this techmap is the carry outputs for synthesis, e.g. might hit the - // fabric. - // - // So we maintain two wire sets, CO_CHAIN is the carry that is for VPR, - // e.g. off fabric dedicated chain. CO is the carry outputs that are - // available to the fabric. - (* force_downto *) - wire [Y_WIDTH-1:0] CO_CHAIN; - (* force_downto *) - wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT}; - - // If carry chain is being initialized to a constant, techmap the constant - // source. Otherwise techmap the fabric source. - generate for (i = 0; i < 1; i = i + 1) begin:slice - CARRY0 #(.CYINIT_FABRIC(1)) carry( - .CI_INIT(CI), - .DI(AA[0]), - .S(S[0]), - .CO_CHAIN(CO_CHAIN[0]), - .CO_FABRIC(CO[0]), - .O(Y[0]) - ); - end endgenerate - - generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice - if(i % 4 == 0) begin - CARRY0 carry ( - .CI(C[i]), - .DI(AA[i]), - .S(S[i]), - .CO_CHAIN(CO_CHAIN[i]), - .CO_FABRIC(CO[i]), - .O(Y[i]) - ); - end - else - begin - CARRY carry ( - .CI(C[i]), - .DI(AA[i]), - .S(S[i]), - .CO_CHAIN(CO_CHAIN[i]), - .CO_FABRIC(CO[i]), - .O(Y[i]) - ); - end - end endgenerate - - generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice - if(i % 4 == 0) begin - CARRY0 top_of_carry ( - .CI(C[i]), - .DI(AA[i]), - .S(S[i]), - .CO_CHAIN(CO_CHAIN[i]), - .O(Y[i]) - ); - end - else - begin - CARRY top_of_carry ( - .CI(C[i]), - .DI(AA[i]), - .S(S[i]), - .CO_CHAIN(CO_CHAIN[i]), - .O(Y[i]) - ); - end - // Turns out CO_FABRIC and O both use [ABCD]MUX, so provide - // a non-congested path to output the top of the carry chain. - // Registering the output of the CARRY block would solve this, but not - // all designs do that. - if((i+1) % 4 == 0) begin - CARRY0 carry_output ( - .CI(CO_CHAIN[i]), - .DI(0), - .S(0), - .O(CO[i]) - ); - end - else - begin - CARRY carry_output ( - .CI(CO_CHAIN[i]), - .DI(0), - .S(0), - .O(CO[i]) - ); - end - end endgenerate - end else begin localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4; diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 801949d22..ec4635ac6 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -18,43 +18,6 @@ * */ -// Convert negative-polarity reset to positive-polarity -(* techmap_celltype = "$_DFF_NN0_" *) -module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_DFF_PN0_" *) -module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_DFF_NN1_" *) -module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_DFF_PN1_" *) -module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule - -(* techmap_celltype = "$__DFFE_NN0" *) -module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$__DFFE_PN0" *) -module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$__DFFE_NN1" *) -module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$__DFFE_PN1" *) -module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule - -(* techmap_celltype = "$__DFFS_NN0_" *) -module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$__DFFS_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$__DFFS_PN0_" *) -module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$__DFFS_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$__DFFS_NN1_" *) -module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$__DFFS_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$__DFFS_PN1_" *) -module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$__DFFS_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule - -(* techmap_celltype = "$__DFFSE_NN0" *) -module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFSE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$__DFFSE_PN0" *) -module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFSE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$__DFFSE_NN1" *) -module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFSE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$__DFFSE_PN1" *) -module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFSE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule - module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; parameter [DEPTH-1:0] INIT = 0; diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index f5850d8a2..4162160bb 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -455,29 +455,6 @@ module CARRY8( assign CO[7] = S[7] ? CO[6] : DI[7]; endmodule -`ifdef _EXPLICIT_CARRY - -module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S); - parameter CYINIT_FABRIC = 0; - wire CI_COMBINE; - if(CYINIT_FABRIC) begin - assign CI_COMBINE = CI_INIT; - end else begin - assign CI_COMBINE = CI; - end - assign CO_CHAIN = S ? CI_COMBINE : DI; - assign CO_FABRIC = S ? CI_COMBINE : DI; - assign O = S ^ CI_COMBINE; -endmodule - -module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S); - assign CO_CHAIN = S ? CI : DI; - assign CO_FABRIC = S ? CI : DI; - assign O = S ^ CI; -endmodule - -`endif - module ORCY (output O, input CI, I); assign O = CI | I; endmodule @@ -2358,6 +2335,8 @@ parameter integer PREG = 1; // The multiplier. wire signed [35:0] P_MULT; +wire signed [17:0] A_MULT; +wire signed [17:0] B_MULT; assign P_MULT = A_MULT * B_MULT; // The cascade output. @@ -2396,8 +2375,6 @@ always @(posedge CLK) begin end // The register enables. -wire signed [17:0] A_MULT; -wire signed [17:0] B_MULT; assign A_MULT = (AREG == 1) ? A_REG : A; assign B_MULT = (BREG == 1) ? B_REG : B_MUX; assign P = (PREG == 1) ? P_REG : P_MULT; @@ -3037,8 +3014,12 @@ endmodule // Virtex 6, Series 7. `ifdef YOSYS -(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG), - lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) *) +(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) +`ifdef ALLOW_WHITEBOX_DSP48E1 + // Do not make DSP48E1 a whitebox for ABC9 even if fully combinatorial, since it is a big complex block + , lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG || INMODEREG || OPMODEREG || ALUMODEREG || CARRYINREG || CARRYINSELREG) +`endif +*) `endif module DSP48E1 ( output [29:0] ACOUT, @@ -3526,11 +3507,15 @@ module DSP48E1 ( if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); `endif end - 2'b10: begin X = P; + 2'b10: + if (PREG == 1) + X = P; + else begin + X = 48'bx; `ifndef YOSYS - if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10"); + $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10"); `endif - end + end 2'b11: X = $signed({Ar2, Br2}); default: X = 48'bx; endcase @@ -3552,20 +3537,36 @@ module DSP48E1 ( case (OPMODEr[6:4]) 3'b000: Z = 48'b0; 3'b001: Z = PCIN; - 3'b010: begin Z = P; + 3'b010: + if (PREG == 1) + Z = P; + else begin + Z = 48'bx; `ifndef YOSYS - if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010"); + $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b010"); `endif - end + end 3'b011: Z = Cr; - 3'b100: begin Z = P; + 3'b100: + if (PREG == 1 && OPMODEr[3:0] === 4'b1000) + Z = P; + else begin + Z = 48'bx; `ifndef YOSYS - if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); - if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100"); + if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); + if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100"); `endif - end + end 3'b101: Z = $signed(PCIN[47:17]); - 3'b110: Z = $signed(P[47:17]); + 3'b110: + if (PREG == 1) + Z = $signed(P[47:17]); + else begin + Z = 48'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b110"); +`endif + end default: Z = 48'bx; endcase end @@ -3591,10 +3592,34 @@ module DSP48E1 ( 3'b001: cin_muxed = ~PCIN[47]; 3'b010: cin_muxed = CARRYCASCIN; 3'b011: cin_muxed = PCIN[47]; - 3'b100: cin_muxed = CARRYCASCOUT; - 3'b101: cin_muxed = ~P[47]; + 3'b100: + if (PREG == 1) + cin_muxed = CARRYCASCOUT; + else begin + cin_muxed = 1'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b100"); +`endif + end + 3'b101: + if (PREG == 1) + cin_muxed = ~P[47]; + else begin + cin_muxed = 1'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b101"); +`endif + end 3'b110: cin_muxed = A24_xnor_B17; - 3'b111: cin_muxed = P[47]; + 3'b111: + if (PREG == 1) + cin_muxed = P[47]; + else begin + cin_muxed = 1'bx; +`ifndef YOSYS + $fatal(1, "PREG must be 1 when CARRYINSEL is 3'b111"); +`endif + end default: cin_muxed = 1'bx; endcase end @@ -4186,4 +4211,3 @@ module RAMB36E1 ( if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 882; endspecify endmodule - diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v new file mode 100644 index 000000000..45d202294 --- /dev/null +++ b/techlibs/xilinx/ff_map.v @@ -0,0 +1,120 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`ifndef _NO_FFS + +// Async reset, enable. + +module \$_DFFE_NP0P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DFFE_PP0P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$_DFFE_NP1P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DFFE_PP1P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Async set and reset, enable. + +module \$_DFFSRE_NPPP_ (input D, C, E, S, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DFFSRE_PPPP_ (input D, C, E, S, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Sync reset, enable. + +module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Latches with reset. + +module \$_DLATCH_NP0_ (input E, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_PP0_ (input E, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_NP1_ (input E, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_PP1_ (input E, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +// Latches with set and reset. + +module \$_DLATCH_NPP_ (input E, S, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_PPP_ (input E, S, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +`endif + diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d0de73f83..0adec57a2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -30,13 +30,13 @@ struct SynthXilinxPass : public ScriptPass { SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { } - void on_register() YS_OVERRIDE + void on_register() override { RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate // to one LUT6 (instead of a LUT5 + LUT2) } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -77,10 +77,6 @@ struct SynthXilinxPass : public ScriptPass log(" write the design to the specified BLIF file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); log("\n"); - log(" -vpr\n"); - log(" generate an output netlist (and BLIF file) suitable for VPR\n"); - log(" (this feature is experimental and incomplete)\n"); - log("\n"); log(" -ise\n"); log(" generate an output netlist suitable for ISE\n"); log("\n"); @@ -142,14 +138,14 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram; + bool flatten, retime, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram; bool abc9, dff; bool flatten_before_abc; int widemux; int lut_size; int widelut_size; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; edif_file.clear(); @@ -157,7 +153,6 @@ struct SynthXilinxPass : public ScriptPass family = "xc7"; flatten = false; retime = false; - vpr = false; ise = false; noiopad = false; noclkbuf = false; @@ -176,7 +171,7 @@ struct SynthXilinxPass : public ScriptPass lut_size = 6; } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { std::string run_from, run_to; clear_flags(); @@ -229,10 +224,6 @@ struct SynthXilinxPass : public ScriptPass nowidelut = true; continue; } - if (args[argidx] == "-vpr") { - vpr = true; - continue; - } if (args[argidx] == "-ise") { ise = true; continue; @@ -337,23 +328,14 @@ struct SynthXilinxPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { std::string lut_size_s = std::to_string(lut_size); if (help_mode) lut_size_s = "[46]"; - std::string ff_map_file; - if (help_mode) - ff_map_file = "+/xilinx/{family}_ff_map.v"; - else if (family == "xc6s") - ff_map_file = "+/xilinx/xc6s_ff_map.v"; - else - ff_map_file = "+/xilinx/xc7_ff_map.v"; if (check_label("begin")) { std::string read_args; - if (vpr) - read_args += " -D_EXPLICIT_CARRY"; read_args += " -lib -specify +/xilinx/cells_sim.v"; run("read_verilog" + read_args); @@ -375,6 +357,8 @@ struct SynthXilinxPass : public ScriptPass run("opt_expr"); run("opt_clean"); run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); run("opt"); if (help_mode) run("wreduce [-keepdc]", "(option for '-widemux')"); @@ -462,8 +446,6 @@ struct SynthXilinxPass : public ScriptPass run("alumacc"); run("share"); run("opt"); - run("fsm"); - run("opt -fast"); run("memory -nomap"); run("opt_clean"); } @@ -522,28 +504,21 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_ffram")) { - // Required for dff2dffs to work. - run("simplemap t:$dff t:$adff t:$mux"); - // Needs to be done before opt -mux_bool happens. - if (help_mode) - run("dff2dffs [-match-init]", "(-match-init for xc6s only)"); - else if (family == "xc6s") - run("dff2dffs -match-init"); - else - run("dff2dffs"); - if (widemux > 0) + if (widemux > 0) { run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover // performs less efficiently - else + } else { run("opt -fast -full"); + } run("memory_map"); } if (check_label("fine")) { - run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); - if (help_mode) - run("muxcover <internal options> ('-widemux' only)"); - else if (widemux > 0) { + if (help_mode) { + run("simplemap t:$mux", "('-widemux' only)"); + run("muxcover <internal options>", "('-widemux' only)"); + } else if (widemux > 0) { + run("simplemap t:$mux"); constexpr int cost_mux2 = 100; std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2); switch (widemux) { @@ -577,8 +552,6 @@ struct SynthXilinxPass : public ScriptPass techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux); if (!nocarry) { techmap_args += " -map +/xilinx/arith_map.v"; - if (vpr) - techmap_args += " -D _EXPLICIT_CARRY"; } run("techmap " + techmap_args); run("opt -fast"); @@ -595,16 +568,22 @@ struct SynthXilinxPass : public ScriptPass run("clean"); } - if (check_label("map_ffs", "('-abc9' only)")) { + if (check_label("map_ffs")) { + if (family == "xc6s") + run("dfflegalize -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r -cell $_DLATCH_?P?_ r", "(for xc6s)"); + else if (family == "xc6v" || family == "xc7" || family == "xcu" || family == "xcup") + run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01", "(for xc6v, xc7, xcu, xcup)"); + else + run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_DFFSRE_?PPP_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01 -cell $_DLATCHSR_?PP_ 01", "(for xc5v and older)"); if (abc9 || help_mode) { if (dff || help_mode) - run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "('-dff' only)"); - run("techmap -map " + ff_map_file); + run("zinit -all w:* t:$_SDFFE_*", "('-dff' only)"); + run("techmap -map +/xilinx/ff_map.v", "('-abc9' only)"); } } if (check_label("map_luts")) { - run("opt_expr -mux_undef"); + run("opt_expr -mux_undef -noclkinv"); if (flatten_before_abc) run("flatten"); if (help_mode) @@ -653,13 +632,13 @@ struct SynthXilinxPass : public ScriptPass } run("clean"); + if (help_mode || !abc9) + run("techmap -map +/xilinx/ff_map.v", "(only if not '-abc9')"); // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')"); std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"; - if (help_mode || !abc9) - techmap_args += stringf(" -map %s", ff_map_file.c_str()); techmap_args += " -D LUT_WIDTH=" + lut_size_s; run("techmap " + techmap_args); if (help_mode) diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v deleted file mode 100644 index c40f446e0..000000000 --- a/techlibs/xilinx/xc6s_ff_map.v +++ /dev/null @@ -1,256 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -// ============================================================================ -// FF mapping for Spartan 6. The primitives used are the same as Series 7, -// but with one major difference: the initial value is implied by the -// primitive type used (FFs with reset pin must have INIT set to 0 or x, FFs -// with set pin must have INIT set to 1 or x). For Yosys primitives without -// set/reset, this means we have to pick the primitive type based on the INIT -// value. - -`ifndef _NO_FFS - -// No reset. - -module \$_DFF_N_ (input D, C, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0)); - else - FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DFF_P_ (input D, C, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0)); - else - FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// No reset, enable. - -module \$_DFFE_NP_ (input D, C, E, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(1'b0)); - else - FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DFFE_PP_ (input D, C, E, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(1'b0)); - else - FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Async reset. - -module \$_DFF_NP0_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); - else - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); - else - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -module \$_DFF_NP1_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); - else - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); - else - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Async reset, enable. - -module \$__DFFE_NP0 (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); - else - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1"); - else - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -module \$__DFFE_NP1 (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); - else - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFE_PP1 (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0"); - else - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Sync reset. - -module \$__DFFS_NP0_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with reset initialized to 1"); - else - FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFS_PP0_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with reset initialized to 1"); - else - FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -module \$__DFFS_NP1_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with set initialized to 0"); - else - FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFS_PP1_ (input D, C, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with set initialized to 0"); - else - FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Sync reset, enable. - -module \$__DFFSE_NP0 (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with reset initialized to 1"); - else - FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFSE_PP0 (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - $error("Spartan 6 doesn't support FFs with reset initialized to 1"); - else - FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -module \$__DFFSE_NP1 (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with set initialized to 0"); - else - FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFSE_PP1 (input D, C, E, R, output Q); - parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b0) - $error("Spartan 6 doesn't support FFs with set initialized to 0"); - else - FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Latches (no reset). - -module \$_DLATCH_N_ (input E, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0)); - else - LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DLATCH_P_ (input E, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) - LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0)); - else - LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0)); - endgenerate - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Latches with reset (TODO). - -`endif - diff --git a/techlibs/xilinx/xc7_dsp_map.v b/techlibs/xilinx/xc7_dsp_map.v index a4256eb92..58df977ec 100644 --- a/techlibs/xilinx/xc7_dsp_map.v +++ b/techlibs/xilinx/xc7_dsp_map.v @@ -33,6 +33,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .B(B), .C(48'b0), .D(25'b0), + .CARRYIN(1'b0), .P(P_48), .INMODE(5'b00000), diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v deleted file mode 100644 index 2bd874457..000000000 --- a/techlibs/xilinx/xc7_ff_map.v +++ /dev/null @@ -1,178 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -// ============================================================================ -// FF mapping for Virtex 6, Series 7 and Ultrascale. These families support -// the following features: -// -// - a CLB flip-flop can be used as a latch or as a flip-flop -// - a CLB flip-flop has the following pins: -// -// - data input -// - clock (or gate for latches) (with optional inversion) -// - clock enable (or gate enable, which is just ANDed with gate — unused by -// synthesis) -// - either a set or a reset input, which (for FFs) can be either -// synchronous or asynchronous (with optional inversion) -// - data output -// -// - a flip-flop also has an initial value, which is set at device -// initialization (or whenever GSR is asserted) - -`ifndef _NO_FFS - -// No reset. - -module \$_DFF_N_ (input D, C, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DFF_P_ (input D, C, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// No reset, enable. - -module \$_DFFE_NP_ (input D, C, E, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DFFE_PP_ (input D, C, E, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Async reset. - -module \$_DFF_NP0_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -module \$_DFF_NP1_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Async reset, enable. - -module \$__DFFE_NP0 (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -module \$__DFFE_NP1 (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFE_PP1 (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Sync reset. - -module \$__DFFS_NP0_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFS_PP0_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -module \$__DFFS_NP1_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFS_PP1_ (input D, C, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Sync reset, enable. - -module \$__DFFSE_NP0 (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFSE_PP0 (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -module \$__DFFSE_NP1 (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$__DFFSE_PP1 (input D, C, E, R, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Latches (no reset). - -module \$_DLATCH_N_ (input E, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule -module \$_DLATCH_P_ (input E, D, output Q); - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0)); - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -// Latches with reset (TODO). - -`endif - diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index c9d63c9f7..365f505fb 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -99,7 +99,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool struct XilinxDffOptPass : public Pass { XilinxDffOptPass() : Pass("xilinx_dffopt", "Xilinx: optimize FF control signal usage") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -113,7 +113,7 @@ struct XilinxDffOptPass : public Pass { log(" Assume a LUT4-based device (instead of a LUT6-based device).\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { log_header(design, "Executing XILINX_DFFOPT pass (optimize FF control signal usage).\n"); |