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-rw-r--r--tests/arch/common/blockram.v45
-rw-r--r--tests/arch/common/lutram.v42
-rw-r--r--tests/arch/common/memory.v21
-rw-r--r--tests/arch/common/memory_attributes/attributes_test.v88
4 files changed, 175 insertions, 21 deletions
diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v
new file mode 100644
index 000000000..dbc6ca65c
--- /dev/null
+++ b/tests/arch/common/blockram.v
@@ -0,0 +1,45 @@
+`default_nettype none
+module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+ (input wire write_enable, clk,
+ input wire [DATA_WIDTH-1:0] data_in,
+ input wire [ADDRESS_WIDTH-1:0] address_in,
+ output wire [DATA_WIDTH-1:0] data_out);
+
+ localparam WORD = (DATA_WIDTH-1);
+ localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+ reg [WORD:0] data_out_r;
+ reg [WORD:0] memory [0:DEPTH];
+
+ always @(posedge clk) begin
+ if (write_enable)
+ memory[address_in] <= data_in;
+ data_out_r <= memory[address_in];
+ end
+
+ assign data_out = data_out_r;
+endmodule // sync_ram_sp
+
+
+`default_nettype none
+module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+ (input wire clk, write_enable,
+ input wire [DATA_WIDTH-1:0] data_in,
+ input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
+ output wire [DATA_WIDTH-1:0] data_out);
+
+ localparam WORD = (DATA_WIDTH-1);
+ localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+ reg [WORD:0] data_out_r;
+ reg [WORD:0] memory [0:DEPTH];
+
+ always @(posedge clk) begin
+ if (write_enable)
+ memory[address_in_w] <= data_in;
+ data_out_r <= memory[address_in_r];
+ end
+
+ assign data_out = data_out_r;
+endmodule // sync_ram_sdp
+
diff --git a/tests/arch/common/lutram.v b/tests/arch/common/lutram.v
new file mode 100644
index 000000000..9534b7619
--- /dev/null
+++ b/tests/arch/common/lutram.v
@@ -0,0 +1,42 @@
+module lutram_1w1r
+#(parameter D_WIDTH=8, A_WIDTH=6)
+(
+ input [D_WIDTH-1:0] data_a,
+ input [A_WIDTH:1] addr_a,
+ input we_a, clk,
+ output reg [D_WIDTH-1:0] q_a
+);
+ // Declare the RAM variable
+ reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
+
+ // Port A
+ always @ (posedge clk)
+ begin
+ if (we_a)
+ ram[addr_a] <= data_a;
+ q_a <= ram[addr_a];
+ end
+endmodule
+
+
+module lutram_1w3r
+#(parameter D_WIDTH=8, A_WIDTH=5)
+(
+ input [D_WIDTH-1:0] data_a, data_b, data_c,
+ input [A_WIDTH:1] addr_a, addr_b, addr_c,
+ input we_a, clk,
+ output reg [D_WIDTH-1:0] q_a, q_b, q_c
+);
+ // Declare the RAM variable
+ reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
+
+ // Port A
+ always @ (posedge clk)
+ begin
+ if (we_a)
+ ram[addr_a] <= data_a;
+ q_a <= ram[addr_a];
+ q_b <= ram[addr_b];
+ q_c <= ram[addr_c];
+ end
+endmodule
diff --git a/tests/arch/common/memory.v b/tests/arch/common/memory.v
deleted file mode 100644
index cb7753f7b..000000000
--- a/tests/arch/common/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
- input [7:0] data_a,
- input [6:1] addr_a,
- input we_a, clk,
- output reg [7:0] q_a
-);
- // Declare the RAM variable
- reg [7:0] ram[63:0];
-
- // Port A
- always @ (posedge clk)
- begin
- if (we_a)
- begin
- ram[addr_a] <= data_a;
- q_a <= data_a;
- end
- q_a <= ram[addr_a];
- end
-endmodule
diff --git a/tests/arch/common/memory_attributes/attributes_test.v b/tests/arch/common/memory_attributes/attributes_test.v
new file mode 100644
index 000000000..275800dd0
--- /dev/null
+++ b/tests/arch/common/memory_attributes/attributes_test.v
@@ -0,0 +1,88 @@
+`default_nettype none
+module block_ram #(parameter DATA_WIDTH=4, ADDRESS_WIDTH=10)
+ (input wire write_enable, clk,
+ input wire [DATA_WIDTH-1:0] data_in,
+ input wire [ADDRESS_WIDTH-1:0] address_in,
+ output wire [DATA_WIDTH-1:0] data_out);
+
+ localparam WORD = (DATA_WIDTH-1);
+ localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+ reg [WORD:0] data_out_r;
+ reg [WORD:0] memory [0:DEPTH];
+
+ always @(posedge clk) begin
+ if (write_enable)
+ memory[address_in] <= data_in;
+ data_out_r <= memory[address_in];
+ end
+
+ assign data_out = data_out_r;
+endmodule // block_ram
+
+`default_nettype none
+module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
+ (input wire write_enable, clk,
+ input wire [DATA_WIDTH-1:0] data_in,
+ input wire [ADDRESS_WIDTH-1:0] address_in,
+ output wire [DATA_WIDTH-1:0] data_out);
+
+ localparam WORD = (DATA_WIDTH-1);
+ localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+ reg [WORD:0] data_out_r;
+ reg [WORD:0] memory [0:DEPTH];
+
+ always @(posedge clk) begin
+ if (write_enable)
+ memory[address_in] <= data_in;
+ data_out_r <= memory[address_in];
+ end
+
+ assign data_out = data_out_r;
+endmodule // distributed_ram
+
+`default_nettype none
+module distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
+ (input wire write_enable, clk,
+ input wire [DATA_WIDTH-1:0] data_in,
+ input wire [ADDRESS_WIDTH-1:0] address_in,
+ output wire [DATA_WIDTH-1:0] data_out);
+
+ localparam WORD = (DATA_WIDTH-1);
+ localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+ reg [WORD:0] data_out_r;
+ (* ram_style = "block" *) reg [WORD:0] memory [0:DEPTH];
+
+ always @(posedge clk) begin
+ if (write_enable)
+ memory[address_in] <= data_in;
+ data_out_r <= memory[address_in];
+ end
+
+ assign data_out = data_out_r;
+endmodule // distributed_ram
+
+`default_nettype none
+module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
+ (input wire write_enable, clk,
+ input wire [DATA_WIDTH-1:0] data_in,
+ input wire [ADDRESS_WIDTH-1:0] address_in,
+ output wire [DATA_WIDTH-1:0] data_out);
+
+ localparam WORD = (DATA_WIDTH-1);
+ localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+ reg [WORD:0] data_out_r;
+ (* synthesis, ram_block *) reg [WORD:0] memory [0:DEPTH];
+
+ always @(posedge clk) begin
+ if (write_enable)
+ memory[address_in] <= data_in;
+ data_out_r <= memory[address_in];
+ end
+
+ assign data_out = data_out_r;
+endmodule // distributed_ram
+
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