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-rw-r--r--tests/arch/common/adffs.v8
-rw-r--r--tests/arch/common/counter.v22
-rw-r--r--tests/arch/common/dffs.v2
-rw-r--r--tests/arch/common/fsm.v102
-rw-r--r--tests/arch/common/mul.v7
-rw-r--r--tests/arch/common/shifter.v28
6 files changed, 93 insertions, 76 deletions
diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
index 576bd81a6..966e7c2b8 100644
--- a/tests/arch/common/adffs.v
+++ b/tests/arch/common/adffs.v
@@ -1,7 +1,9 @@
module adff( input d, clk, clr, output reg q );
+`ifndef NO_INIT
initial begin
q = 0;
end
+`endif
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
@@ -10,9 +12,11 @@ module adff( input d, clk, clr, output reg q );
endmodule
module adffn( input d, clk, clr, output reg q );
+`ifndef NO_INIT
initial begin
q = 0;
end
+`endif
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
@@ -21,9 +25,11 @@ module adffn( input d, clk, clr, output reg q );
endmodule
module dffs( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
initial begin
q = 0;
end
+`endif
always @( posedge clk )
if ( pre )
q <= 1'b1;
@@ -32,9 +38,11 @@ module dffs( input d, clk, pre, clr, output reg q );
endmodule
module ndffnr( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
initial begin
q = 0;
end
+`endif
always @( negedge clk )
if ( !clr )
q <= 1'b0;
diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v
index 9746fd701..1e0a13dc9 100644
--- a/tests/arch/common/counter.v
+++ b/tests/arch/common/counter.v
@@ -1,11 +1,11 @@
-module top ( out, clk, reset );
- output [7:0] out;
- input clk, reset;
- reg [7:0] out;
-
- always @(posedge clk, posedge reset)
- if (reset)
- out <= 8'b0;
- else
- out <= out + 1;
-endmodule
+module top ( out, clk, reset );
+ output [7:0] out;
+ input clk, reset;
+ reg [7:0] out;
+
+ always @(posedge clk, posedge reset)
+ if (reset)
+ out <= 8'b0;
+ else
+ out <= out + 1;
+endmodule
diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v
index 636252d16..0c607af50 100644
--- a/tests/arch/common/dffs.v
+++ b/tests/arch/common/dffs.v
@@ -4,9 +4,11 @@ module dff ( input d, clk, output reg q );
endmodule
module dffe( input d, clk, en, output reg q );
+`ifndef NO_INIT
initial begin
q = 0;
end
+`endif
always @( posedge clk )
if ( en )
q <= d;
diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v
index 9d3fbb64a..cf1c21a58 100644
--- a/tests/arch/common/fsm.v
+++ b/tests/arch/common/fsm.v
@@ -1,51 +1,51 @@
- module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
- input clock,reset,req_0,req_1;
- output gnt_0,gnt_1;
- wire clock,reset,req_0,req_1;
- reg gnt_0,gnt_1;
-
- parameter SIZE = 3;
- parameter IDLE = 3'b001;
- parameter GNT0 = 3'b010;
- parameter GNT1 = 3'b100;
- parameter GNT2 = 3'b101;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
- state <= #1 IDLE;
- gnt_0 <= 0;
- gnt_1 <= 0;
- end
- else
- case(state)
- IDLE : if (req_0 == 1'b1) begin
- state <= #1 GNT0;
- gnt_0 <= 1;
- end else if (req_1 == 1'b1) begin
- gnt_1 <= 1;
- state <= #1 GNT0;
- end else begin
- state <= #1 IDLE;
- end
- GNT0 : if (req_0 == 1'b1) begin
- state <= #1 GNT0;
- end else begin
- gnt_0 <= 0;
- state <= #1 IDLE;
- end
- GNT1 : if (req_1 == 1'b1) begin
- state <= #1 GNT2;
- gnt_1 <= req_0;
- end
- GNT2 : if (req_0 == 1'b1) begin
- state <= #1 GNT1;
- gnt_1 <= req_1;
- end
- default : state <= #1 IDLE;
- endcase
- end
-endmodule
+ module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
+ input clock,reset,req_0,req_1;
+ output gnt_0,gnt_1;
+ wire clock,reset,req_0,req_1;
+ reg gnt_0,gnt_1;
+
+ parameter SIZE = 3;
+ parameter IDLE = 3'b001;
+ parameter GNT0 = 3'b010;
+ parameter GNT1 = 3'b100;
+ parameter GNT2 = 3'b101;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ gnt_0 <= 0;
+ gnt_1 <= 0;
+ end
+ else
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ gnt_0 <= 1;
+ end else if (req_1 == 1'b1) begin
+ gnt_1 <= 1;
+ state <= #1 GNT0;
+ end else begin
+ state <= #1 IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ end else begin
+ gnt_0 <= 0;
+ state <= #1 IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ state <= #1 GNT2;
+ gnt_1 <= req_0;
+ end
+ GNT2 : if (req_0 == 1'b1) begin
+ state <= #1 GNT1;
+ gnt_1 <= req_1;
+ end
+ default : state <= #1 IDLE;
+ endcase
+ end
+endmodule
diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v
index 437a91cfc..baed64fcd 100644
--- a/tests/arch/common/mul.v
+++ b/tests/arch/common/mul.v
@@ -1,9 +1,10 @@
module top
+#(parameter X_WIDTH=6, Y_WIDTH=6, A_WIDTH=12)
(
- input [5:0] x,
- input [5:0] y,
+ input [X_WIDTH-1:0] x,
+ input [Y_WIDTH-1:0] y,
- output [11:0] A,
+ output [A_WIDTH-1:0] A,
);
assign A = x * y;
endmodule
diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v
index cace3b588..06e63c9af 100644
--- a/tests/arch/common/shifter.v
+++ b/tests/arch/common/shifter.v
@@ -1,11 +1,17 @@
-module top(out, clk, in);
- output [7:0] out;
- input signed clk, in;
- reg signed [7:0] out = 0;
-
- always @(posedge clk)
- begin
- out <= out >> 1;
- out[7] <= in;
- end
-endmodule
+module top(out, clk, in);
+ output [7:0] out;
+ input signed clk, in;
+ reg signed [7:0] out;
+
+`ifndef NO_INIT
+ initial begin
+ out = 0;
+ end
+`endif
+
+ always @(posedge clk)
+ begin
+ out <= out >> 1;
+ out[7] <= in;
+ end
+endmodule
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