1 files changed, 33 insertions, 0 deletions
diff --git a/tests/arch/fabulous/regfile.ys b/tests/arch/fabulous/regfile.ys
new file mode 100644
index 000000000..8d1eedef0
--- /dev/null
+++ b/tests/arch/fabulous/regfile.ys
@@ -0,0 +1,33 @@
+read_verilog <<EOT
+module sync_sync(input clk, we, input [4:0] aw, aa, ab, input [3:0] wd, output reg [3:0] ra, rb);
+	reg [3:0] mem[0:31];
+	always @(posedge clk)
+		if (we) mem[aw] <= wd;
+	always @(posedge clk)
+		ra <= mem[aa];
+	always @(posedge clk)
+		rb <= mem[ab];
+endmodule
+EOT
+
+synth_fabulous -top sync_sync
+cd sync_sync
+select -assert-count 1 t:RegFile_32x4
+
+design -reset
+
+read_verilog <<EOT
+module async_sync(input clk, we, input [4:0] aw, aa, ab, input [3:0] wd, output reg [3:0] ra, rb);
+	reg [3:0] mem[0:31];
+	always @(posedge clk)
+		if (we) mem[aw] <= wd;
+	always @(posedge clk)
+		ra <= mem[aa];
+	always @(*)
+		rb <= mem[ab];
+endmodule
+EOT
+
+synth_fabulous -top async_sync
+cd async_sync
+select -assert-count 1 t:RegFile_32x4