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Diffstat (limited to 'tests/arch/ice40/latches.ys')
| -rw-r--r-- | tests/arch/ice40/latches.ys | 33 |
1 files changed, 27 insertions, 6 deletions
diff --git a/tests/arch/ice40/latches.ys b/tests/arch/ice40/latches.ys index 708734e44..b06dd630b 100644 --- a/tests/arch/ice40/latches.ys +++ b/tests/arch/ice40/latches.ys @@ -1,12 +1,33 @@ -read_verilog latches.v +read_verilog ../common/latches.v +design -save read +hierarchy -top latchp proc -flatten # Can't run any sort of equivalence check because latches are blown to LUTs -#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +synth_ice40 +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ice40 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + -#design -load preopt +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ice40 -cd top -select -assert-count 4 t:SB_LUT4 +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:SB_LUT4 + select -assert-none t:SB_LUT4 %% t:* %D |