diff options
Diffstat (limited to 'tests/arch/ice40')
28 files changed, 867 insertions, 0 deletions
diff --git a/tests/arch/ice40/.gitignore b/tests/arch/ice40/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/arch/ice40/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys new file mode 100644 index 000000000..578ec0803 --- /dev/null +++ b/tests/arch/ice40/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 +select -assert-count 6 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D + diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys new file mode 100644 index 000000000..e5dbabb43 --- /dev/null +++ b/tests/arch/ice40/adffs.ys @@ -0,0 +1,39 @@ +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFR +select -assert-none t:SB_DFFR %% t:* %D + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFR +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFSS +select -assert-none t:SB_DFFSS %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFNSR +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/bug1597.ys b/tests/arch/ice40/bug1597.ys new file mode 100644 index 000000000..b7983cfa4 --- /dev/null +++ b/tests/arch/ice40/bug1597.ys @@ -0,0 +1,72 @@ +read_verilog <<EOT +module top ( + input CLK, PIN_1, PIN_2, PIN_3, PIN_4, PIN_5, + PIN_6, PIN_7, PIN_8, PIN_9, PIN_10, PIN_11, PIN_12, PIN_13, PIN_25, + output USBPU, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18, + PIN_19, PIN_20, PIN_21, PIN_22, PIN_23, PIN_24, +); + assign USBPU = 0; + + wire[5:0] parOut; + wire[5:0] chrg; + + assign PIN_14 = parOut[0]; + assign PIN_15 = parOut[1]; + assign PIN_16 = parOut[2]; + assign PIN_17 = parOut[3]; + assign PIN_18 = parOut[4]; + assign PIN_19 = parOut[5]; + assign chrg[0] = PIN_3; + assign chrg[1] = PIN_4; + assign chrg[2] = PIN_5; + assign chrg[3] = PIN_6; + assign chrg[4] = PIN_7; + assign chrg[5] = PIN_8; + + SSCounter6o sc6(PIN_1, CLK, PIN_2, PIN_9, chrg, parOut); + +endmodule + +module SSCounter6 (input wire rst, clk, adv, jmp, input wire [5:0] in, output reg[5:0] out); + always @(posedge clk, posedge rst) + if (rst) out <= 0; + else if (adv || jmp) out <= jmp ? in : out + 1; +endmodule + +// Optimized 6 bit counter, it should takes 7 cells. +/* b[5:1] /* b[0] +1010101010101010 in 1010101010101010 in +1100110011001100 jmp 1100110011001100 jmp +1111000011110000 loop 1111000011110000 loop +1111111100000000 carry 1111111100000000 - +---------------------- ---------------------- +1000101110111000 out 1000101110001011 out + 8 B B 8 8 B 8 B +*/ +module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output wire[5:0] out); + wire[4:0] co; + wire[5:0] lo; + wire ien; + SB_LUT4 #(.LUT_INIT(16'hFFF0)) lien (ien, 0, 0, adv, jmp); + SB_CARRY c0 (co[0], jmp, out[0], 1), + c1 (co[1], jmp, out[1], co[0]), + c2 (co[2], jmp, out[2], co[1]), + c3 (co[3], jmp, out[3], co[2]), + c4 (co[4], jmp, out[4], co[3]); + SB_DFFER d0 (out[0], clk, ien, rst, lo[0]), + d1 (out[1], clk, ien, rst, lo[1]), + d2 (out[2], clk, ien, rst, lo[2]), + d3 (out[3], clk, ien, rst, lo[3]), + d4 (out[4], clk, ien, rst, lo[4]), + d5 (out[5], clk, ien, rst, lo[5]); + SB_LUT4 #(.LUT_INIT(16'h8B8B)) l0 (lo[0], in[0], jmp, out[0], 0); + SB_LUT4 #(.LUT_INIT(16'h8BB8)) l1 (lo[1], in[1], jmp, out[1], co[0]); + SB_LUT4 #(.LUT_INIT(16'h8BB8)) l2 (lo[2], in[2], jmp, out[2], co[1]); + SB_LUT4 #(.LUT_INIT(16'h8BB8)) l3 (lo[3], in[3], jmp, out[3], co[2]); + SB_LUT4 #(.LUT_INIT(16'h8BB8)) l4 (lo[4], in[4], jmp, out[4], co[3]); + SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]); +endmodule +EOT +hierarchy -top top +flatten +equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40 diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys new file mode 100644 index 000000000..8438cb979 --- /dev/null +++ b/tests/arch/ice40/bug1598.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module led_blink ( + input clk, + output ledc + ); + + reg [6:0] led_counter = 0; + always @( posedge clk ) begin + led_counter <= led_counter + 1; + end + assign ledc = !led_counter[ 6:3 ]; + +endmodule +EOT +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9 diff --git a/tests/arch/ice40/bug1626.ys b/tests/arch/ice40/bug1626.ys new file mode 100644 index 000000000..27b6fb5e8 --- /dev/null +++ b/tests/arch/ice40/bug1626.ys @@ -0,0 +1,217 @@ +read_ilang <<EOT +# Generated by Yosys 0.9+1706 (git sha1 58ab9f60, clang 6.0.0-1ubuntu2 -fPIC -Os) +autoidx 2815 +attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:9" +attribute \cells_not_processed 1 +attribute \dynports 1 +module \ahb_async_sram_halfwidth + parameter \DEPTH + parameter \W_ADDR + parameter \W_BYTEADDR + parameter \W_DATA + parameter \W_SRAM_ADDR + parameter \W_SRAM_DATA + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\addr_lsb[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\hready_r[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\long_dphase[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire width 16 $0\rdata_buf[15:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\read_dph[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + wire $0\write_dph[0:0] + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63" + wire width 32 $add$../hdl/mem/ahb_async_sram_halfwidth.v:63$2433_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62" + wire width 16 $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56" + wire $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2450_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2451_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2452_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2453_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2454_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2455_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2456_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2457_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2458_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2459_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:118$2444_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:133" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:133$2449_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2461_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2463_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:58$2425_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2426_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2427_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2429_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91" + wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:104" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:104$2442_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:118$2443_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:125" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:125$2446_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:132$2447_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:59$2428_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:81" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:81$2438_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:83" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:83$2439_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91" + wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:91$2440_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118" + wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:118$2445_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132" + wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:132$2448_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59" + wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139" + wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2460_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139" + wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2462_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54" + wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63" + wire width 16 $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54" + wire width 8 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2419_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54" + wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2420_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55" + wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56" + wire width 32 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:56$2423_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63" + wire width 32 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:63$2432_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:65" + wire width 16 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:50" + wire \addr_lsb + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:24" + wire width 32 \ahbls_haddr + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:28" + wire width 3 \ahbls_hburst + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:30" + wire \ahbls_hmastlock + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:29" + wire width 4 \ahbls_hprot + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:32" + wire width 32 \ahbls_hrdata + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:22" + wire \ahbls_hready + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:21" + wire \ahbls_hready_resp + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:23" + wire \ahbls_hresp + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:27" + wire width 3 \ahbls_hsize + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:26" + wire width 2 \ahbls_htrans + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:31" + wire width 32 \ahbls_hwdata + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:25" + wire \ahbls_hwrite + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56" + wire \aphase_full_width + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55" + wire width 2 \bytemask + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54" + wire width 2 \bytemask_noshift + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:17" + wire \clk + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:46" + wire \hready_r + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:47" + wire \long_dphase + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:64" + wire width 16 \rdata_buf + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:49" + wire \read_dph + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:18" + wire \rst_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:34" + wire width 11 \sram_addr + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:39" + wire width 2 \sram_byte_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:36" + wire \sram_ce_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:35" + wire width 16 \sram_dq + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:38" + wire \sram_oe_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:61" + wire width 16 \sram_q + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62" + wire width 16 \sram_rdata + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63" + wire width 16 \sram_wdata + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:37" + wire \sram_we_n + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58" + wire \we_next + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:48" + wire \write_dph + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71" + process $proc$../hdl/mem/ahb_async_sram_halfwidth.v:71$2436 + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72" + switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y + case 1'1 + case + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78" + switch \ahbls_hready + case 1'1 + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79" + switch \ahbls_htrans [1] + case 1'1 + case + end + case + attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91" + switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y + case 1'1 + case + end + end + end + sync posedge \clk + sync negedge \rst_n + end + connect \ahbls_hresp 1'0 + connect \bytemask_noshift $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y + connect \bytemask $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y + connect \aphase_full_width $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y + connect \we_next $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y + connect \sram_rdata $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y + connect \sram_wdata $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y + connect \ahbls_hrdata { \sram_rdata $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y } + connect \ahbls_hready_resp \hready_r +end +EOT + +synth_ice40 -abc2 -abc9 diff --git a/tests/arch/ice40/bug1644.il.gz b/tests/arch/ice40/bug1644.il.gz Binary files differnew file mode 100644 index 000000000..363c510ef --- /dev/null +++ b/tests/arch/ice40/bug1644.il.gz diff --git a/tests/arch/ice40/bug1644.ys b/tests/arch/ice40/bug1644.ys new file mode 100644 index 000000000..5950f0e3c --- /dev/null +++ b/tests/arch/ice40/bug1644.ys @@ -0,0 +1,2 @@ +read_ilang bug1644.il.gz +synth_ice40 -top top -dsp -json adc_dac_pass_through.json -run :map_bram diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys new file mode 100644 index 000000000..7bbc4f2c3 --- /dev/null +++ b/tests/arch/ice40/counter.ys @@ -0,0 +1,11 @@ +read_verilog ../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys new file mode 100644 index 000000000..b28a5a91f --- /dev/null +++ b/tests/arch/ice40/dffs.ys @@ -0,0 +1,19 @@ +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFE +select -assert-none t:SB_DFFE %% t:* %D
\ No newline at end of file diff --git a/tests/arch/ice40/dpram.v b/tests/arch/ice40/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/arch/ice40/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1<<addr_width)-1:0] +/* synthesis syn_ramstyle = "no_rw_check" */ ; +always @(posedge wclk) // Write memory. +begin +if (write_en) +mem[waddr] <= din; // Using write address bus. +end +always @(posedge rclk) // Read memory. +begin +dout <= mem[raddr]; // Using read address bus. +end +endmodule diff --git a/tests/arch/ice40/dpram.ys b/tests/arch/ice40/dpram.ys new file mode 100644 index 000000000..4f6a253ea --- /dev/null +++ b/tests/arch/ice40/dpram.ys @@ -0,0 +1,15 @@ +read_verilog dpram.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:SB_RAM40_4K +select -assert-none t:SB_RAM40_4K %% t:* %D diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys new file mode 100644 index 000000000..223ba070e --- /dev/null +++ b/tests/arch/ice40/fsm.ys @@ -0,0 +1,16 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 4 t:SB_DFF +select -assert-count 2 t:SB_DFFESR +select -assert-count 15 t:SB_LUT4 +select -assert-none t:SB_DFFESR t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys new file mode 100644 index 000000000..250273859 --- /dev/null +++ b/tests/arch/ice40/ice40_dsp.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module top(input [15:0] a, b, output [31:0] o1, o2, o5); +SB_MAC16 m1 (.A(a), .B(16'd1234), .O(o1)); +assign o2 = a * 16'd0; +wire [31:0] o3, o4; +SB_MAC16 m2 (.A(a), .B(b), .O(o3)); +assign o4 = a * b; +SB_MAC16 m3 (.A(a), .B(b), .O(o5)); +endmodule +EOT +ice40_dsp diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys new file mode 100644 index 000000000..71b68431e --- /dev/null +++ b/tests/arch/ice40/ice40_opt.ys @@ -0,0 +1,118 @@ +read_verilog -icells -formal <<EOT +module top(input CI, I0, output [1:0] CO, output O); + wire A = 1'b0, B = 1'b0; + \$__ICE40_CARRY_WRAPPER #( + // A[0]: 1010 1010 1010 1010 + // A[1]: 1100 1100 1100 1100 + // A[2]: 1111 0000 1111 0000 + // A[3]: 1111 1111 0000 0000 + .LUT(~16'b 0110_1001_1001_0110), + .I3_IS_CI(1'b1) + ) u0 ( + .A(A), + .B(B), + .CI(CI), + .I0(I0), + .I3(1'bx), + .CO(CO[0]), + .O(O) + ); + SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1])); +endmodule +EOT + +equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt +design -load postopt +select -assert-count 1 t:* +select -assert-count 1 t:$lut + +# https://github.com/YosysHQ/yosys/issues/1543 +design -reset +read_verilog <<EOT +module delay_element (input wire clk, input wire reset, input wire enable, + input wire chainin, output wire chainout, output reg latch); + + + reg const_zero = 0; + reg const_one = 1; + + wire delay_tap; + + + //carry logic + (* keep *) SB_CARRY carry ( .CO(chainout), .I0(const_zero), + .I1(const_one), .CI(chainin)); + + + //flip flop latch + (* keep *) SB_DFFER flipflop( .Q(latch), .C(clk), .E(enable), + .D(delay_tap), .R(reset)); + + + //LUT table + // the LUT should just echo the carry in (I3) + // carry I0 = LUT I1 + // carry I1 = LUT I2 + // carry in = LUT I3 + // LUT_INIT[0] = 0 + // LUT_INIT[1] = 0 + // LUT_INIT[2] = 0 + // LUT_INIT[3] = 0 + // LUT_INIT[4] = 0 + // LUT_INIT[5] = 0 + // LUT_INIT[6] = 0 + // LUT_INIT[7] = 0 + // LUT_INIT[8] = 1 + // LUT_INIT[9] = 1 + // LUT_INIT[10] = 1 + // LUT_INIT[11] = 1 + // LUT_INIT[12] = 1 + // LUT_INIT[13] = 1 + // LUT_INIT[14] = 1 + // LUT_INIT[15] = 1 + + (* keep *) SB_LUT4 lut( .O(delay_tap), .I0(const_zero), .I1(const_zero), + .I2(const_one), .I3(chainin)); + + //TODO: is this the right way round?? + defparam lut.LUT_INIT=16'hFF00; + + +endmodule // delay_element +EOT + +synth_ice40 +select -assert-count 1 t:SB_LUT4 +select -assert-count 1 t:SB_CARRY +select -assert-count 1 t:SB_CARRY a:keep %i +select -assert-count 1 t:SB_CARRY c:carry %i + + +design -reset +read_verilog -icells <<EOT +module top(input I3, I2, I1, I0, output O, O2); + SB_LUT4 #( + .LUT_INIT(8'b 1001_0110) + ) u0 ( + .I0(I0), + .I1(I1), + .I2(I2), + .I3(), + .O(O) + ); + wire CO; + \$__ICE40_CARRY_WRAPPER #( + .LUT(~8'b 1001_0110), + .I3_IS_CI(1'b0) + ) u1 ( + .A(1'b0), + .B(1'b0), + .CI(1'b0), + .I0(), + .I3(), + .CO(CO), + .O(O2) + ); +endmodule +EOT +ice40_opt diff --git a/tests/arch/ice40/ice40_wrapcarry.ys b/tests/arch/ice40/ice40_wrapcarry.ys new file mode 100644 index 000000000..fb9fccc3a --- /dev/null +++ b/tests/arch/ice40/ice40_wrapcarry.ys @@ -0,0 +1,54 @@ +read_verilog <<EOT +module top(input A, B, CI, output O, CO); + SB_CARRY carry ( + .I0(A), + .I1(B), + .CI(CI), + .CO(CO) + ); + SB_LUT4 #( + .LUT_INIT(16'b 0110_1001_1001_0110) + ) adder ( + .I0(1'b0), + .I1(A), + .I2(B), + .I3(1'b0), + .O(O) + ); +endmodule +EOT + +ice40_wrapcarry +select -assert-count 1 t:$__ICE40_CARRY_WRAPPER + +design -reset +read_verilog <<EOT +module top(input A, B, CI, output O, CO); + (* foo = "bar", answer = 42, keep=0 *) + SB_CARRY carry ( + .I0(A), + .I1(B), + .CI(CI), + .CO(CO) + ); + (* keep, blah="blah", answer = 43 *) + SB_LUT4 #( + .LUT_INIT(16'b 0110_1001_1001_0110) + ) adder ( + .I0(1'b0), + .I1(A), + .I2(B), + .I3(1'b0), + .O(O) + ); +endmodule +EOT + +ice40_wrapcarry +select -assert-count 1 t:$__ICE40_CARRY_WRAPPER +select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d +select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i + +ice40_wrapcarry -unwrap +select -assert-count 1 c:carry a:src=<<EOT:3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i +select -assert-count 1 c:adder a:src=<<EOT:10 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i diff --git a/tests/arch/ice40/latches.ys b/tests/arch/ice40/latches.ys new file mode 100644 index 000000000..b06dd630b --- /dev/null +++ b/tests/arch/ice40/latches.ys @@ -0,0 +1,33 @@ +read_verilog ../common/latches.v +design -save read + +hierarchy -top latchp +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ice40 +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ice40 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ice40 +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/logic.ys b/tests/arch/ice40/logic.ys new file mode 100644 index 000000000..7432f5b1f --- /dev/null +++ b/tests/arch/ice40/logic.ys @@ -0,0 +1,7 @@ +read_verilog ../common/logic.v +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 9 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/lutram.ys b/tests/arch/ice40/lutram.ys new file mode 100644 index 000000000..1ba40f8ec --- /dev/null +++ b/tests/arch/ice40/lutram.ys @@ -0,0 +1,15 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:SB_RAM40_4K +select -assert-none t:SB_RAM40_4K %% t:* %D diff --git a/tests/arch/ice40/macc.v b/tests/arch/ice40/macc.v new file mode 100644 index 000000000..6f68e7500 --- /dev/null +++ b/tests/arch/ice40/macc.v @@ -0,0 +1,47 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77]. +*/ +module top(clk,a,b,c,set); +parameter A_WIDTH = 6 /*4*/; +parameter B_WIDTH = 6 /*3*/; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin + if(set) + begin + reg_tmp_c <= 0; + end + else + begin + reg_tmp_c <= a * b + c; + end +end +endmodule + +module top2(clk,a,b,c,hold); +parameter A_WIDTH = 6 /*4*/; +parameter B_WIDTH = 6 /*3*/; +input hold; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg signed [A_WIDTH-1:0] reg_a; +reg signed [B_WIDTH-1:0] reg_b; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin + if (!hold) begin + reg_a <= a; + reg_b <= b; + reg_tmp_c <= reg_a * reg_b + c; + end +end +endmodule diff --git a/tests/arch/ice40/macc.ys b/tests/arch/ice40/macc.ys new file mode 100644 index 000000000..fd30e79c5 --- /dev/null +++ b/tests/arch/ice40/macc.ys @@ -0,0 +1,25 @@ +read_verilog macc.v +proc +design -save read + +hierarchy -top top +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_MAC16 +select -assert-none t:SB_MAC16 %% t:* %D + +design -load read +hierarchy -top top2 + +#equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check + +equiv_opt -run :prove -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +clk2fflogic +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -set-init-zero -seq 4 -verify -prove-asserts -show-ports miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top2 # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_MAC16 +select -assert-none t:SB_MAC16 %% t:* %D diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys new file mode 100644 index 000000000..b8c3eb941 --- /dev/null +++ b/tests/arch/ice40/mul.ys @@ -0,0 +1,7 @@ +read_verilog ../common/mul.v +hierarchy -top top +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_MAC16 +select -assert-none t:SB_MAC16 %% t:* %D diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys new file mode 100644 index 000000000..99822391d --- /dev/null +++ b/tests/arch/ice40/mux.ys @@ -0,0 +1,40 @@ +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v new file mode 100644 index 000000000..71459fe38 --- /dev/null +++ b/tests/arch/ice40/rom.v @@ -0,0 +1,19 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74]. +*/ +module top(data, addr); +output [3:0] data; // Note: this prompts a Yosys warning, but + // vendor doc does not contain 'reg' +input [4:0] addr; +always @(addr) begin +case (addr) +0 : data = 'h4; +1 : data = 'h9; +2 : data = 'h1; +15 : data = 'h8; +16 : data = 'h1; +17 : data = 'h0; +default : data = 'h0; +endcase +end +endmodule diff --git a/tests/arch/ice40/rom.ys b/tests/arch/ice40/rom.ys new file mode 100644 index 000000000..41d214e2a --- /dev/null +++ b/tests/arch/ice40/rom.ys @@ -0,0 +1,8 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 5 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/run-test.sh b/tests/arch/ice40/run-test.sh new file mode 100755 index 000000000..bf19b887d --- /dev/null +++ b/tests/arch/ice40/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/ice40/shifter.ys b/tests/arch/ice40/shifter.ys new file mode 100644 index 000000000..08ea64f3d --- /dev/null +++ b/tests/arch/ice40/shifter.ys @@ -0,0 +1,9 @@ +read_verilog ../common/shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/arch/ice40/tribuf.ys b/tests/arch/ice40/tribuf.ys new file mode 100644 index 000000000..10cded954 --- /dev/null +++ b/tests/arch/ice40/tribuf.ys @@ -0,0 +1,11 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D |