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-rw-r--r--tests/arch/machxo2/dffs.ys8
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys
index 83a79a9d6..29dcafe23 100644
--- a/tests/arch/machxo2/dffs.ys
+++ b/tests/arch/machxo2/dffs.ys
@@ -6,8 +6,8 @@ proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
-select -assert-count 1 t:FACADE_FF
-select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D
+select -assert-count 1 t:TRELLIS_FF
+select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D
design -load read
hierarchy -top dffe
@@ -15,5 +15,5 @@ proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
-select -assert-count 2 t:FACADE_FF t:LUT4
-select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D
+select -assert-count 2 t:TRELLIS_FF t:LUT4
+select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D