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-rw-r--r--tests/arch/xilinx/add_sub.ys2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys
index f06e7fa01..9dbddce47 100644
--- a/tests/arch/xilinx/add_sub.ys
+++ b/tests/arch/xilinx/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check