diff options
Diffstat (limited to 'tests/arch/xilinx/blockram.ys')
| -rw-r--r-- | tests/arch/xilinx/blockram.ys | 32 |
1 files changed, 4 insertions, 28 deletions
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index ed743cf44..c2b7aede7 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -2,7 +2,7 @@ ### currently. Checking instance counts instead. # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 read_verilog ../common/blockram.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 1 sync_ram_sdp synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 @@ -35,7 +35,7 @@ chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 -select -assert-count 4 t:RAM128X1D +select -assert-count 4 t:RAM64M # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset @@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp @@ -58,23 +58,7 @@ select -assert-count 1 t:RAMB18E1 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 -setattr -set ram_block 1 m:memory -synth_xilinx -top sync_ram_sdp -noiopad -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 -setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory -synth_xilinx -top sync_ram_sdp -noiopad -cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set logic_block 1 m:memory synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp @@ -87,11 +71,3 @@ setattr -set ram_style "block" m:memory synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 -setattr -set ram_block 1 m:memory -synth_xilinx -top sync_ram_sdp -noiopad -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 |