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-rw-r--r--tests/arch/xilinx/mul.ys2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys
index 66a06efdc..d76814966 100644
--- a/tests/arch/xilinx/mul.ys
+++ b/tests/arch/xilinx/mul.ys
@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check