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-rw-r--r--tests/arch/xilinx/xilinx_srl.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v
index bc2a15ab2..29920da41 100644
--- a/tests/arch/xilinx/xilinx_srl.v
+++ b/tests/arch/xilinx/xilinx_srl.v
@@ -29,7 +29,7 @@ endmodule
module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
-parameter DEPTH = 1;
+parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;