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-rw-r--r--tests/arch/ecp5/mux.ys6
-rw-r--r--tests/arch/ecp5/opt_lut_ins.ys32
-rw-r--r--tests/arch/efinix/mux.ys6
-rw-r--r--tests/arch/gowin/mux.ys8
-rw-r--r--tests/arch/ice40/bug1597.ys72
-rw-r--r--tests/arch/ice40/bug1644.il.gzbin0 -> 25669 bytes
-rw-r--r--tests/arch/ice40/bug1644.ys2
-rw-r--r--tests/arch/ice40/ice40_dsp.ys11
-rw-r--r--tests/arch/ice40/ice40_opt.ys57
-rw-r--r--tests/arch/xilinx/add_sub.ys14
-rw-r--r--tests/arch/xilinx/bug1462.ys11
-rw-r--r--tests/arch/xilinx/dffs.ys22
-rw-r--r--tests/arch/xilinx/fsm.ys19
-rw-r--r--tests/arch/xilinx/lutram.ys20
-rw-r--r--tests/arch/xilinx/mux_lut4.ys51
-rw-r--r--tests/arch/xilinx/opt_lut_ins.ys25
-rw-r--r--tests/arch/xilinx/tribuf.sh5
-rw-r--r--tests/arch/xilinx/xilinx_dsp.ys11
18 files changed, 337 insertions, 35 deletions
diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
index 22866832d..92463aa32 100644
--- a/tests/arch/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys
@@ -39,8 +39,8 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 12 t:L6MUX21
-select -assert-count 34 t:LUT4
-select -assert-count 17 t:PFUMX
+select -assert-count 8 t:L6MUX21
+select -assert-count 26 t:LUT4
+select -assert-count 12 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
diff --git a/tests/arch/ecp5/opt_lut_ins.ys b/tests/arch/ecp5/opt_lut_ins.ys
new file mode 100644
index 000000000..2bc546912
--- /dev/null
+++ b/tests/arch/ecp5/opt_lut_ins.ys
@@ -0,0 +1,32 @@
+read_ilang << EOF
+
+module \top
+
+ wire input 1 \A
+ wire input 2 \B
+ wire input 3 \C
+ wire input 4 \D
+
+ wire output 5 \Z
+
+ cell \LUT4 $0
+ parameter \INIT 16'1111110011000000
+ connect \A \A
+ connect \B \B
+ connect \C \C
+ connect \D \D
+ connect \Z \Z
+ end
+end
+
+EOF
+
+read_verilog -lib +/ecp5/cells_sim.v
+
+equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech ecp5
+
+design -load postopt
+
+select -assert-count 1 top/t:LUT4
+select -assert-count 0 top/w:A %co top/t:LUT4 %i
+select -assert-count 1 top/w:B %co top/t:LUT4 %i
diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys
index b46f641e1..67006b6f2 100644
--- a/tests/arch/efinix/mux.ys
+++ b/tests/arch/efinix/mux.ys
@@ -16,7 +16,7 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 2 t:EFX_LUT4
+#select -assert-count 2 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D
@@ -26,7 +26,7 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 5 t:EFX_LUT4
+#select -assert-count 5 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D
@@ -36,6 +36,6 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 12 t:EFX_LUT4
+select -assert-max 12 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
index afad29a89..33b092284 100644
--- a/tests/arch/gowin/mux.ys
+++ b/tests/arch/gowin/mux.ys
@@ -18,13 +18,13 @@ proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 4 t:LUT4
+select -assert-count 4 t:LUT*
select -assert-count 2 t:MUX2_LUT5
select -assert-count 1 t:MUX2_LUT6
select -assert-count 6 t:IBUF
select -assert-count 1 t:OBUF
-select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux8
@@ -35,7 +35,7 @@ cd mux8 # Constrain all select calls below inside the top module
select -assert-count 11 t:IBUF
select -assert-count 1 t:OBUF
-select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux16
@@ -46,4 +46,4 @@ cd mux16 # Constrain all select calls below inside the top module
select -assert-count 20 t:IBUF
select -assert-count 1 t:OBUF
-select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:GND t:VCC t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/ice40/bug1597.ys b/tests/arch/ice40/bug1597.ys
new file mode 100644
index 000000000..b7983cfa4
--- /dev/null
+++ b/tests/arch/ice40/bug1597.ys
@@ -0,0 +1,72 @@
+read_verilog <<EOT
+module top (
+ input CLK, PIN_1, PIN_2, PIN_3, PIN_4, PIN_5,
+ PIN_6, PIN_7, PIN_8, PIN_9, PIN_10, PIN_11, PIN_12, PIN_13, PIN_25,
+ output USBPU, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18,
+ PIN_19, PIN_20, PIN_21, PIN_22, PIN_23, PIN_24,
+);
+ assign USBPU = 0;
+
+ wire[5:0] parOut;
+ wire[5:0] chrg;
+
+ assign PIN_14 = parOut[0];
+ assign PIN_15 = parOut[1];
+ assign PIN_16 = parOut[2];
+ assign PIN_17 = parOut[3];
+ assign PIN_18 = parOut[4];
+ assign PIN_19 = parOut[5];
+ assign chrg[0] = PIN_3;
+ assign chrg[1] = PIN_4;
+ assign chrg[2] = PIN_5;
+ assign chrg[3] = PIN_6;
+ assign chrg[4] = PIN_7;
+ assign chrg[5] = PIN_8;
+
+ SSCounter6o sc6(PIN_1, CLK, PIN_2, PIN_9, chrg, parOut);
+
+endmodule
+
+module SSCounter6 (input wire rst, clk, adv, jmp, input wire [5:0] in, output reg[5:0] out);
+ always @(posedge clk, posedge rst)
+ if (rst) out <= 0;
+ else if (adv || jmp) out <= jmp ? in : out + 1;
+endmodule
+
+// Optimized 6 bit counter, it should takes 7 cells.
+/* b[5:1] /* b[0]
+1010101010101010 in 1010101010101010 in
+1100110011001100 jmp 1100110011001100 jmp
+1111000011110000 loop 1111000011110000 loop
+1111111100000000 carry 1111111100000000 -
+---------------------- ----------------------
+1000101110111000 out 1000101110001011 out
+ 8 B B 8 8 B 8 B
+*/
+module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output wire[5:0] out);
+ wire[4:0] co;
+ wire[5:0] lo;
+ wire ien;
+ SB_LUT4 #(.LUT_INIT(16'hFFF0)) lien (ien, 0, 0, adv, jmp);
+ SB_CARRY c0 (co[0], jmp, out[0], 1),
+ c1 (co[1], jmp, out[1], co[0]),
+ c2 (co[2], jmp, out[2], co[1]),
+ c3 (co[3], jmp, out[3], co[2]),
+ c4 (co[4], jmp, out[4], co[3]);
+ SB_DFFER d0 (out[0], clk, ien, rst, lo[0]),
+ d1 (out[1], clk, ien, rst, lo[1]),
+ d2 (out[2], clk, ien, rst, lo[2]),
+ d3 (out[3], clk, ien, rst, lo[3]),
+ d4 (out[4], clk, ien, rst, lo[4]),
+ d5 (out[5], clk, ien, rst, lo[5]);
+ SB_LUT4 #(.LUT_INIT(16'h8B8B)) l0 (lo[0], in[0], jmp, out[0], 0);
+ SB_LUT4 #(.LUT_INIT(16'h8BB8)) l1 (lo[1], in[1], jmp, out[1], co[0]);
+ SB_LUT4 #(.LUT_INIT(16'h8BB8)) l2 (lo[2], in[2], jmp, out[2], co[1]);
+ SB_LUT4 #(.LUT_INIT(16'h8BB8)) l3 (lo[3], in[3], jmp, out[3], co[2]);
+ SB_LUT4 #(.LUT_INIT(16'h8BB8)) l4 (lo[4], in[4], jmp, out[4], co[3]);
+ SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]);
+endmodule
+EOT
+hierarchy -top top
+flatten
+equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40
diff --git a/tests/arch/ice40/bug1644.il.gz b/tests/arch/ice40/bug1644.il.gz
new file mode 100644
index 000000000..363c510ef
--- /dev/null
+++ b/tests/arch/ice40/bug1644.il.gz
Binary files differ
diff --git a/tests/arch/ice40/bug1644.ys b/tests/arch/ice40/bug1644.ys
new file mode 100644
index 000000000..5950f0e3c
--- /dev/null
+++ b/tests/arch/ice40/bug1644.ys
@@ -0,0 +1,2 @@
+read_ilang bug1644.il.gz
+synth_ice40 -top top -dsp -json adc_dac_pass_through.json -run :map_bram
diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys
new file mode 100644
index 000000000..250273859
--- /dev/null
+++ b/tests/arch/ice40/ice40_dsp.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [15:0] a, b, output [31:0] o1, o2, o5);
+SB_MAC16 m1 (.A(a), .B(16'd1234), .O(o1));
+assign o2 = a * 16'd0;
+wire [31:0] o3, o4;
+SB_MAC16 m2 (.A(a), .B(b), .O(o3));
+assign o4 = a * b;
+SB_MAC16 m3 (.A(a), .B(b), .O(o5));
+endmodule
+EOT
+ice40_dsp
diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index 5186d4800..71b68431e 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -1,24 +1,4 @@
read_verilog -icells -formal <<EOT
-module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
- parameter LUT = 0;
- SB_CARRY carry (
- .I0(A),
- .I1(B),
- .CI(CI),
- .CO(CO)
- );
- \$lut #(
- .WIDTH(4),
- .LUT(LUT)
- ) lut (
- .A({I0,A,B,I3}),
- .Y(O)
- );
-endmodule
-EOT
-design -stash unmap
-
-read_verilog -icells -formal <<EOT
module top(input CI, I0, output [1:0] CO, output O);
wire A = 1'b0, B = 1'b0;
\$__ICE40_CARRY_WRAPPER #(
@@ -26,13 +6,14 @@ module top(input CI, I0, output [1:0] CO, output O);
// A[1]: 1100 1100 1100 1100
// A[2]: 1111 0000 1111 0000
// A[3]: 1111 1111 0000 0000
- .LUT(~16'b 0110_1001_1001_0110)
+ .LUT(~16'b 0110_1001_1001_0110),
+ .I3_IS_CI(1'b1)
) u0 (
.A(A),
.B(B),
.CI(CI),
.I0(I0),
- .I3(CI),
+ .I3(1'bx),
.CO(CO[0]),
.O(O)
);
@@ -40,7 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
endmodule
EOT
-equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
+equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*
select -assert-count 1 t:$lut
@@ -105,3 +86,33 @@ select -assert-count 1 t:SB_LUT4
select -assert-count 1 t:SB_CARRY
select -assert-count 1 t:SB_CARRY a:keep %i
select -assert-count 1 t:SB_CARRY c:carry %i
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input I3, I2, I1, I0, output O, O2);
+ SB_LUT4 #(
+ .LUT_INIT(8'b 1001_0110)
+ ) u0 (
+ .I0(I0),
+ .I1(I1),
+ .I2(I2),
+ .I3(),
+ .O(O)
+ );
+ wire CO;
+ \$__ICE40_CARRY_WRAPPER #(
+ .LUT(~8'b 1001_0110),
+ .I3_IS_CI(1'b0)
+ ) u1 (
+ .A(1'b0),
+ .B(1'b0),
+ .CI(1'b0),
+ .I0(),
+ .I3(),
+ .CO(CO),
+ .O(O2)
+ );
+endmodule
+EOT
+ice40_opt
diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys
index 70cfe81a3..6be9a73a3 100644
--- a/tests/arch/xilinx/add_sub.ys
+++ b/tests/arch/xilinx/add_sub.ys
@@ -1,11 +1,23 @@
read_verilog ../common/add_sub.v
hierarchy -top top
proc
+design -save orig
+
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
-select -assert-count 16 t:LUT2
+select -assert-count 8 t:LUT2
select -assert-count 2 t:CARRY4
select -assert-none t:LUT2 t:CARRY4 %% t:* %D
+design -load orig
+
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+stat
+select -assert-count 8 t:LUT2
+select -assert-count 6 t:MUXCY
+select -assert-count 8 t:XORCY
+select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
diff --git a/tests/arch/xilinx/bug1462.ys b/tests/arch/xilinx/bug1462.ys
new file mode 100644
index 000000000..15cab5121
--- /dev/null
+++ b/tests/arch/xilinx/bug1462.ys
@@ -0,0 +1,11 @@
+read_verilog << EOF
+module top(...);
+input wire [31:0] A;
+output wire [31:0] P;
+
+assign P = A * 32'h12300000;
+
+endmodule
+EOF
+
+synth_xilinx
diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys
index dc764b033..deaf16bd6 100644
--- a/tests/arch/xilinx/dffs.ys
+++ b/tests/arch/xilinx/dffs.ys
@@ -8,7 +8,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
-
select -assert-none t:BUFG t:FDRE %% t:* %D
@@ -20,6 +19,27 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
+select -assert-none t:BUFG t:FDRE %% t:* %D
+
+
+design -load read
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
+select -assert-none t:BUFG t:FDRE %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index a464fcfdb..fec4c6082 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -3,6 +3,8 @@ hierarchy -top fsm
proc
flatten
+design -save orig
+
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
@@ -17,3 +19,20 @@ select -assert-count 1 t:LUT2
select -assert-count 3 t:LUT5
select -assert-count 1 t:LUT6
select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
+
+design -load orig
+
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 6 t:FDRE
+select -assert-count 1 t:LUT1
+select -assert-count 3 t:LUT3
+select -assert-count 6 t:LUT4
+select -assert-count 6 t:MUXF5
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys
index 3f127a77e..cc7354501 100644
--- a/tests/arch/xilinx/lutram.ys
+++ b/tests/arch/xilinx/lutram.ys
@@ -135,3 +135,23 @@ select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 2 t:RAM64M
select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
+
+
+design -reset
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r -chparam A_WIDTH 4
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd lutram_1w1r
+select -assert-count 1 t:BUFG
+select -assert-count 8 t:FDRE
+select -assert-count 8 t:RAM16X1D
+select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
diff --git a/tests/arch/xilinx/mux_lut4.ys b/tests/arch/xilinx/mux_lut4.ys
new file mode 100644
index 000000000..3e3256993
--- /dev/null
+++ b/tests/arch/xilinx/mux_lut4.ys
@@ -0,0 +1,51 @@
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+
+select -assert-none t:LUT3 %% t:* %D
+
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 4 t:LUT1
+select -assert-count 2 t:MUXF5
+select -assert-count 1 t:MUXF6
+
+select -assert-none t:LUT1 t:MUXF5 t:MUXF6 %% t:* %D
+
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 4 t:LUT1
+select -assert-count 3 t:LUT4
+select -assert-count 2 t:MUXF5
+select -assert-count 1 t:MUXF6
+
+select -assert-none t:LUT1 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D
+
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-max 32 t:LUT*
+select -assert-max 8 t:MUXF6
+select -assert-max 4 t:MUXF7
+
+select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 %% t:* %D
diff --git a/tests/arch/xilinx/opt_lut_ins.ys b/tests/arch/xilinx/opt_lut_ins.ys
new file mode 100644
index 000000000..a01d02179
--- /dev/null
+++ b/tests/arch/xilinx/opt_lut_ins.ys
@@ -0,0 +1,25 @@
+read_ilang << EOF
+
+module \top
+
+ wire width 4 input 1 \A
+
+ wire output 2 \O
+
+ cell \LUT4 $0
+ parameter \INIT 16'1111110011000000
+ connect \I0 \A [0]
+ connect \I1 \A [1]
+ connect \I2 \A [2]
+ connect \I3 \A [3]
+ connect \O \O
+ end
+end
+
+EOF
+
+equiv_opt -assert -map +/xilinx/cells_sim.v opt_lut_ins -tech xilinx
+
+design -load postopt
+
+select -assert-count 1 t:LUT3
diff --git a/tests/arch/xilinx/tribuf.sh b/tests/arch/xilinx/tribuf.sh
new file mode 100644
index 000000000..636aed12a
--- /dev/null
+++ b/tests/arch/xilinx/tribuf.sh
@@ -0,0 +1,5 @@
+! ../../../yosys ../common/tribuf.v -qp "synth_xilinx"
+../../../yosys ../common/tribuf.v -qp "synth_xilinx -iopad; \
+select -assert-count 2 t:IBUF; \
+select -assert-count 1 t:INV; \
+select -assert-count 1 t:OBUFT"
diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys
new file mode 100644
index 000000000..3b9f52930
--- /dev/null
+++ b/tests/arch/xilinx/xilinx_dsp.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5);
+DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1));
+assign o2 = a * 16'd0;
+wire [42:0] o3, o4;
+DSP48E1 m2 (.A(a), .B(b), .P(o3));
+assign o4 = a * b;
+DSP48E1 m3 (.A(a), .B(b), .P(o5));
+endmodule
+EOT
+xilinx_dsp
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-31 18:25:07 +0000