4 files changed, 35 insertions, 6 deletions
diff --git a/tests/arch/ecp5/bug1630.ys b/tests/arch/ecp5/bug1630.ys
index b419fb9bb..63df1ad5b 100644
--- a/tests/arch/ecp5/bug1630.ys
+++ b/tests/arch/ecp5/bug1630.ys
@@ -1,2 +1,2 @@
 read_ilang bug1630.il.gz
-abc9 -lut +/ecp5/abc9_5g.lut
+abc9 -lut 4
diff --git a/tests/arch/ice40/ice40_wrapcarry.ys b/tests/arch/ice40/ice40_wrapcarry.ys
index fb9fccc3a..74319c480 100644
--- a/tests/arch/ice40/ice40_wrapcarry.ys
+++ b/tests/arch/ice40/ice40_wrapcarry.ys
@@ -50,5 +50,5 @@ select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
 select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i
 
 ice40_wrapcarry -unwrap
-select -assert-count 1 c:carry a:src=<<EOT:3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
-select -assert-count 1 c:adder a:src=<<EOT:10 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i
+select -assert-count 1 c:carry a:src=<<EOT:3.11-8.3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
+select -assert-count 1 c:adder a:src=<<EOT:12.4-18.3 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i
diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh
index 5292d1615..170078a7f 100755
--- a/tests/arch/run-test.sh
+++ b/tests/arch/run-test.sh
@@ -2,12 +2,23 @@
 
 set -e
 
+declare -A defines=( ["ice40"]="ICE40_HX ICE40_LP ICE40_U" )
+
 echo "Running syntax check on arch sim models"
 for arch in ../../techlibs/*; do
 	find $arch -name cells_sim.v | while read path; do
-		echo -n "Test $path ->"
-		iverilog -t null -I$arch $path
-		echo " ok"
+		arch_name=$(basename -- $arch)
+		if [ "${defines[$arch_name]}" ]; then
+			for def in ${defines[$arch_name]}; do
+				echo -n "Test $path -D$def ->"
+				iverilog -t null -I$arch -D$def $path
+				echo " ok"
+			done
+		else
+			echo -n "Test $path ->"
+			iverilog -t null -I$arch $path
+			echo " ok"
+		fi
 	done
 done
 
diff --git a/tests/arch/xilinx/bug1480.ys b/tests/arch/xilinx/bug1480.ys
new file mode 100644
index 000000000..84faea08a
--- /dev/null
+++ b/tests/arch/xilinx/bug1480.ys
@@ -0,0 +1,18 @@
+read_verilog << EOF
+module top(...);
+
+input signed [17:0] A;
+input signed [17:0] B;
+output X;
+output Y;
+
+wire [35:0] P;
+assign P = A * B;
+
+assign X = P[0];
+assign Y = P[35];
+
+endmodule
+EOF
+
+synth_xilinx