1 files changed, 18 insertions, 0 deletions
diff --git a/tests/arch/xilinx/bug1480.ys b/tests/arch/xilinx/bug1480.ys
new file mode 100644
index 000000000..84faea08a
--- /dev/null
+++ b/tests/arch/xilinx/bug1480.ys
@@ -0,0 +1,18 @@
+read_verilog << EOF
+module top(...);
+
+input signed [17:0] A;
+input signed [17:0] B;
+output X;
+output Y;
+
+wire [35:0] P;
+assign P = A * B;
+
+assign X = P[0];
+assign Y = P[35];
+
+endmodule
+EOF
+
+synth_xilinx