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-read_verilog logic.v
-hierarchy -top top
-proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 9 t:LUT4
-select -assert-none t:LUT4 %% t:* %D