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Diffstat (limited to 'tests/ice40/add_sub.ys')
| -rw-r--r-- | tests/ice40/add_sub.ys | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys deleted file mode 100644 index 4a998d98d..000000000 --- a/tests/ice40/add_sub.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 11 t:SB_LUT4 -select -assert-count 6 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D - |